Staff Signal Integrity Engineer
$209,100 - $282,900 USD yearly
Originally posted 28 October 2026 by the employer.
About the role
Arm Holdings is seeking a Staff Signal Integrity Engineer to drive signal integrity (SI) design, simulation, optimization, and validation for AI Superchip and data center computing platforms. This position focuses on high-speed interconnects across silicon, packaging, and system platforms to ensure electrical performance and signaling.
What you'll do
- Drive SI design, modeling, simulation, and validation across SoC, advanced 2.5D/3D packaging, PCB, and system-level interconnects.
- Perform high-speed channel analysis and optimization for DDR5/LPDDR, PCIe/CXL, Ethernet, die-to-die (D2D), and SerDes interfaces.
- Develop and validate electromagnetic (EM), S-parameter, IBIS/IBIS-AMI, and behavioral models for chip-to-chip and chip-to-memory interfaces.
- Lead signal integrity optimization, including insertion loss, return loss, crosstalk, impedance discontinuities, equalization, and BER-based eye-margin analysis.
- Collaborate with silicon PHY, package, PCB, architecture, and validation teams to drive SI design guidelines, simulation-to-silicon correlation, and electrical sign-off.
- Support packaging technologies, including chiplets, interposers, high-density substrates, and heterogeneous integration.
What you'll need
- BS/MS/Ph.D. in Electrical Engineering or a related field.
- 8+ years of experience in high-speed signal integrity engineering, semiconductor packaging, or system-level electrical design.
- Expertise in SI simulation and 3D electromagnetic modeling tools such as Ansys HFSS, SIwave, Keysight ADS, or equivalent.
- Solid understanding of high-speed I/O signaling, transmission lines, S-parameters, crosstalk, equalization, and timing/BER analysis.
- Experience with packaging, DDR/LPDDR memory interfaces, PCIe/CXL, and high-speed SerDes technologies.
Nice to have
- Experience with AI/HPC supercomputing platforms, chiplet integration, package-to-board co-design, silicon bring-up, and simulation-to-measurement correlation.
Skills: Signal Integrity, HFSS, SerDes, PCIe, S-parameters, 2.5D/3D packaging
More semiconductor jobs: Arm Holdings jobs · Signal integrity jobs
This role has been open 5 days — well below the 76-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
250
|
Median days open
76 d
|
Category median salary (all employers)
$203k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Arm Holdings | All employers we track in this specialty (250 roles · 48 employers) |
|---|---|---|
| Open roles in this specialty | 3 | 250 |
| Open roles in the wider Analog & Mixed-Signal family | 5 | 1483 · 106 employers |
| Median days open | 5 d | 76 d (−71 d vs this employer) |
| Median salary (USD postings) | — | $203k |
Skills observed across this category: Signal Integrity, HFSS, SerDes, PCIe, S-parameters, 2.5D/3D packaging
Who's hiring in this category
- Synopsys · 34 open roles · median 37 d
- AMD · 26 open roles · median 49 d
- Cadence Design Systems · 21 open roles · median 147 d
- Qualcomm · 17 open roles · median 81 d
- NVIDIA · 16 open roles · median 208 d
- Micron Technology · 12 open roles · median 47 d
How we counted: 250 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 48 employers tracked in the SemiconductorJobs index, counted 3 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.