Staff Signal Integrity Engineer - Bangalore, India
Originally posted 19 August 2026 by the employer.
About the role
This role involves individual contribution within the CHS Signal Integrity organization, responsible for end-to-end SI/PI architecture, analysis, and signoff for mobile, compute, Automotive, and various connectivity platforms.
What you'll do
- Own end-to-end SI/PI closure for programs from pre-silicon to post-silicon and production.
- Define design targets and layout guidelines for high-speed interfaces.
- Ensure SI/PI alignment with product KPIs (performance, yield, power, cost).
- Drive new IP co-design across IC/IO/PHY, package, and PCB.
- Ensure compliance to standards (JEDEC, PCI-SIG, MIPI, IEEE).
- Lead debug of eye collapse / jitter margin issues, crosstalk, power noise, and silicon-package-board interactions.
What you'll need
- 12 years in Signal Integrity / Power Integrity / High-speed systems.
- Proven ownership of multiple tapeouts or high-volume products.
- Deep expertise in Transmission line theory, EM fundamentals, SI/PI interactions, and jitter/noise coupling.
- Hands-on experience with HFSS, ADS, Sigrity, CST, SIwave, HSPICE.
- Hands-on experience with VNA, TDR, real-time scopes.
- Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or related field and 4+ years of Hardware Engineering or related work experience OR Master's degree and 3+ years OR PhD and 2+ years.
Nice to have
- Experience with packaging technologies like FCBGA, 2.5D/3D.
- Experience with Data center, Compute and Servers products.
- Track record of Patents, standards contributions, or published work in internal/external conferences.
Skills: SI/PI closure, high-speed interfaces, PCIe Gen4/5/6/7, LPDDR4/5/6, HFSS, ADS, Sigrity
This role has been open 41 days — well below the 76-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
239
|
Median days open
76 d
|
Median salary
$177k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (239 roles · 49 employers) |
|---|---|---|
| Open roles in this specialty | 20 | 239 |
| Open roles in the wider Analog & Mixed-Signal family | 75 | 1385 · 107 employers |
| Median days open | 58 d | 76 d (−18 d vs this employer) |
| Median salary (USD postings) | — | $177k |
Skills observed across this category: SI/PI closure, high-speed interfaces, PCIe Gen4/5/6/7, LPDDR4/5/6, HFSS, ADS, Sigrity
Who's hiring in this category
- AMD · 28 open roles · median 64 d
- Synopsys · 26 open roles · median 44 d
- Qualcomm (this employer) · 20 open roles · median 58 d
- Cadence Design Systems · 18 open roles · median 181 d
- Apple · 12 open roles · median 7 d
- NVIDIA · 11 open roles · median 116 d
How we counted: 239 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 49 employers tracked in the SemiconductorJobs index, counted 30 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.