Staff Semiconductor Power Engineer (ICB4) - USA-CA San Jose Innovation Drive, United States
$121,900 - $195,000 USD yearly
Originally posted 10 July 2026 by the employer — open 72 days.
About the role
What you'll do
- Lead the complete power lifecycle for complex SoCs, from architectural power definition to silicon validation.
- Conduct dynamic and leakage power analysis at RTL, Gate-level, and Post-layout stages using industry-standard EDA tools.
- Architect, develop, and maintain advanced power analysis flows, automation scripts, and methodologies.
- Identify power bottlenecks and drive active power reduction strategies (e.g., clock gating, power gating, dynamic voltage and frequency scaling).
- Partner with physical design and systems teams on power grid (PDN) sign-off, IR/EM drop analysis, thermal, and packaging constraints.
What you'll need
- Proven track record in semiconductor power definition, estimation, and optimization for complex SoCs or high-performance IPs.
- Strong hands-on experience with industry-standard power analysis and sign-off tools (e.g., Synopsys Pt-PX / PrimePower, Ansys RedHawk, Cadence Joules, or PowerArtist).
- Deep understanding of modern low-power design intents and formats (UPF/CPF), CMOS device physics, and power reduction techniques.
- Proficiency in leveraging AI coding assistants to generate, debug, and optimize scripts (Python, Tcl, Perl) for workflow automation and data parsing.
- Bachelor’s (plus 8 years) or Master’s degree (plus 6 years) in Electrical Engineering, Computer Engineering, or a related field.
Nice to have
- Direct experience taping out designs in advanced semiconductor technology nodes (e.g., 7nm, 5nm, 3nm or below).
- Familiarity with thermal modeling, power delivery network (PDN) design, and voltage drop (IR/EM) mitigation.
- Experience correlating pre-silicon power estimates with post-silicon laboratory measurements.
Skills: power definition, analysis, optimization, power reduction strategies, clock gating, power gating
This role has been open 71 days — exactly the 71-day median for Power Electronics roles.
Power Electronics · Power Management
|
Open roles in category
71
|
Median days open
71 d
|
Median salary
$169k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Broadcom | All employers we track in this specialty (71 roles · 25 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 71 |
| Open roles in the wider Analog & Mixed-Signal family | 41 | 1337 · 105 employers |
| Median days open | 71 d | 71 d (same as this employer) |
| Median salary (USD postings) | — | $169k |
Skills observed across this category: power definition, analysis, optimization, power reduction strategies, clock gating, power gating
Who's hiring in this category
- Renesas Electronics · 15 open roles · median 75 d
- Qualcomm · 8 open roles · median 38 d
- Analog Devices · 6 open roles · median 81 d
- Monolithic Power Systems · 6 open roles · median 184 d
- AMD · 5 open roles · median 89 d
- Infineon Technologies · 5 open roles · median 72 d
How we counted: 71 open Power Electronics (Power Management) roles from 25 employers tracked in the SemiconductorJobs index, counted 20 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.