Originally posted 18 September 2026 by the employer — open 0 days.
About the role
This role involves physical implementation tasks from floor-plan to physical verification, including timing closure, crosstalk analysis, and EM/IR.
What you'll do
- Involve in Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR.
- Handle different PNR tools such as Synopsys Design Compiler, ICC2, ICC, Fusion Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk.
- Involve in Physical design, STA, timing closure, and author methodology scripts in Tcl, Perl and/or Python.
- Work on projects at 16nm, 14nm, 12nm, and sub-10nm process nodes.
What you'll need
- Good knowledge in Physical design, STA, methodology scripts (Tcl), knowledge on Perl, Python.
- Hands-on experience on 16nm, 14nm, 12nm, and sub-10nm projects.
- Bachelors or Masters degree in computer engineering/Electrical Engineering.
Nice to have
- 10 years or more of professional experience in the semiconductor industry.
- Experience in FinFET & Dual Patterning nodes such as 16/14/12 and sub-10nm nodes.
- High-frequency design experience.
- Excellent physical design and timing background.
- MNC experience.
- Familiarity with all Design areas and tools and solid understanding of design/technology interactions.
- Good understanding of computer organization/architecture.
- Exposure/understanding on RTL.
Skills: floor-plan, physical implementation, CTS, timing closure, physical verification
This role has been open 0 days — well below the 57-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
601
|
Median days open
57 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (601 roles · 78 employers) |
|---|---|---|
| Open roles in this specialty | 35 | 601 |
| Open roles in the wider Physical Implementation family | 59 | 1379 · 105 employers |
| Median days open | 38 d | 57 d (−19 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: floor-plan, physical implementation, CTS, timing closure, physical verification
Who's hiring in this category
- Qualcomm · 103 open roles · median 42 d
- Broadcom · 38 open roles · median 67 d
- NVIDIA · 38 open roles · median 48 d
- AMD (this employer) · 34 open roles · median 41 d
- Synopsys · 28 open roles · median 57 d
- Renesas Electronics · 25 open roles · median 44 d
How we counted: 601 open Physical Design (Physical Design) roles from 78 employers tracked in the SemiconductorJobs index, counted 18 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.