Staff Physical Design Engineer, HBM - Richardson, TX, United States
Originally posted 25 August 2026 by the employer.
Drive backend implementation of high‑performance, low‑power digital logic for High‑Bandwidth Memory (HBM) products.
About the role
As a Staff Physical Design Engineer, HBM, you will drive backend implementation of high‑performance, low‑power digital logic used in advanced memory products. This role focuses on backend implementation from Netlist to GDSII, with an emphasis on timing closure, power integrity, and manufacturability.
What you'll do
- Own and execute physical design implementation from synthesized netlist through GDSII, including floorplanning, placement, clock tree synthesis, routing, and physical signoff
- Perform and drive timing closure across multiple modes, corners, and scenarios using industry‑standard STA tools
- Analyze and resolve congestion, timing, IR drop, EM, and power integrity issues
- Implement and validate low‑power design techniques, including multiple/isolated power domains, power gating, and UPF/CPF‑based power intent
- Execute physical verification (DRC/LVS/ANT/DFM) and support signoff flows
- Use scripting and automation (TCL, Python, etc.) to improve productivity, quality, and flow robustness
What you'll need
- Strong understanding of the RTL‑to‑GDSII physical design flow, including floorplanning, place & route, clock distribution, and timing analysis and closure
- Experience with full‑chip integration, partitioning, and budgeting
- Knowledge of low‑power architectures, including DVFS, power gating, and multi‑voltage designs
- Proficiency in scripting/programming (TCL, Python, Perl, Shell scripting)
- Experience in validating Power Distribution Network (PDN), IR/EM
- Bachelor's degree in EE with 7+ years experience in a related field
Nice to have
- Experience with advanced technology nodes
- Experience with high‑frequency, high‑density designs and complex clocking schemes
- Familiarity with memory, HBM, or datapath‑intensive designs
- Experience in 3D-IC technology, methodology, advanced packaging and thermal considerations
Skills: physical design, RTL-to-GDSII, timing closure, HBM, low-power design
This role has been open 51 days — well below the 61-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
661
|
Median days open
61 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (661 roles · 80 employers) |
|---|---|---|
| Open roles in this specialty | 26 | 661 |
| Open roles in the wider Physical Implementation family | 75 | 1459 · 108 employers |
| Median days open | 81 d | 61 d (+20 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: physical design, RTL-to-GDSII, timing closure, HBM, low-power design
Who's hiring in this category
- Qualcomm · 123 open roles · median 44 d
- AMD · 59 open roles · median 22 d
- NVIDIA · 39 open roles · median 69 d
- Synopsys · 37 open roles · median 29 d
- Broadcom · 34 open roles · median 94 d
- Intel Corporation · 30 open roles · median 12 d
How we counted: 661 open Physical Design (Physical Design) roles from 80 employers tracked in the SemiconductorJobs index, counted 15 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.