Staff NAND ECC and Media Architecture Engineer

Develop LDPC and BCH error correction technologies and architectures for NAND Flash memory.

Originally posted 12 November 2026 by the employer.

About the role

This role develops NAND error correction and decoding technologies, including LDPC/BCH, hard/soft decoding, and channel/LLR estimation. You will develop and evaluate algorithms and architectures across NAND, ASIC, firmware, and system teams.

What you'll do

• Develop ECC strategies and integration solutions, evaluating the impact of BCH, LDPC, and other solutions on area, latency, power consumption, and error correction capabilities.
• Analyze NAND channel characteristics and develop and evaluate advanced error-handling techniques.
• Evaluate ECC impact on system-level metrics.
• Explore ECC and data-processing architectures for NAND and AI/storage products.

What you'll need

• 5+ years of background in error-correcting codes or communications/information theory.
• MS or PhD in Electrical Engineering, Computer Engineering, or related field.
• Extensive experience translating algorithms into implementable hardware or firmware architectures.

Nice to have

• Experience in NAND Flash or other non-volatile memory technologies.
• Familiarity with SSD/controller architecture and firmware.
• Good understanding of Claude or Agentic AI or willingness to learn and help develop efficient workflows.

Skills: ECC, LDPC, BCH, NAND flash, error correction, media architecture

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