Staff Modeling Architect - Austin, Texas, United States

Originally posted 4 September 2026 by the employer — open 17 days.

Neurophos uses silicon photonics and an active, programmable metasurface to perform matrix multiplications.

About the role

This staff-level Modeling Architect role builds the path from a production model or application to performance and energy numbers, and a functional model for software boot-up before tape-out. This architecture will deliver up to 100 times the energy efficiency of existing solutions while significantly improving performance for large-scale AI inference.

What you'll do

• Bring up inference workloads such as dense and Mixture of Experts (MoE) transformers, attention, KV cache, expert routing, quantization, and hybrid/SSM models.
• Bind Hugging Face and PyTorch workloads to the programming model and runtime, then run them on the functional model.
• Co-design tiling, scheduling, the instruction set architecture (ISA), SRAM and HBM hierarchy, network-on-chip (NoC) traffic, and multi-chip mapping.
• Run roofline and limiter analysis and design space exploration across microarchitecture options.
• Develop Python energy and latency models in NumPy, Pandas, and Matplotlib that cover operators, tiling, SRAM and HBM traffic, and optical GEMM and vector-unit time.
• Implement bit-accurate C++ functional models of optical GEMM, SRAM vector processors, dataflow engines, and HBM, including narrow arithmetic.
• Contribute to the C++ event-driven simulation kernel itself, including coroutines, timed components, and traces.
• Implement cycle-approximate and cycle-accurate performance, power, and area (PPA) models, and align them with RTL through Verilator, SystemVerilog, and co-simulation.
• Keep numbers consistent across roofline, limiter, performance model, and RTL simulation of the same workload.
• Set the modeling methodology for a workload area.
• Maintain the interface and register specs as the source of truth for generating the C++ and SystemVerilog views, and mentor engineers.

What you'll need

• BS, MS, or PhD in Computer Engineering, Electrical Engineering, Computer Science, or equivalent practical experience.
• 8+ years of experience in hardware modeling, functional modeling, performance modeling, performance simulation, or accelerator performance analysis.
• Track record of shipping a model or study that another team depended on (architecture, compiler, customer, or silicon).
• Judgment to pick the right method for a given question among roofline, limiter analysis, analytical performance models, trace-driven simulation, transaction-level modeling (TLM), and RTL simulation.
• Strong grounding in computer architecture, microarchitecture, memory systems, and AI accelerators (GPU, TPU, NPU, or custom SoC).
• Modern C++ (C++17 or later) for functional models, performance models, and simulation infrastructure.
• Python for models, analysis, and plots, including NumPy, Pandas, and Matplotlib.
• Experience working inside a discrete-event, cycle-approximate, or cycle-accurate simulator such as SystemC, gem5, SST, or a custom kernel.
• Ability to build an LLM or accelerator workload from a model card or paper, covering prefill and decode, MoE, GEMM tiling, and quantization.

Nice to have

• PhD in Computer Engineering, Electrical Engineering, or Computer Science.
• Hardware/software co-design alongside compiler, runtime, or ISA work, including MLIR, TVM, XLA, ONNX, operator fusion, or graph compilers.
• Experience modifying or extending a simulation kernel, or correlating an analytical model against silicon, vendor datasheets, or measured datacenter GPUs and inference accelerators.
• Familiarity with TLM 2.x, Verilator, SystemVerilog, DPI, or UVM.
• Familiarity with HBM, DRAM controllers, cache, SRAM, network-on-chip (NoC), AXI, DMA, and scratchpad memory.
• Power modeling with McPAT, CACTI, or a custom flow, plus FPGA prototyping or hardware emulation.

Skills: optical inference accelerator, hardware/software co-design, performance modeling, functional modeling, SystemVerilog