Staff Mixed-Signal Verification – Analog IP - Allen, TX, United States
Originally posted 1 September 2026 by the employer.
Verify analog and mixed-signal IP integrated into digital-on-top SoC environments on the Treo platform.
About the role
This role involves verifying analog and mixed-signal IP integrated into digital-on-top SoC environments. You will focus on developing and executing mixed-signal verification solutions for the Treo platform, a high-performance analog and mixed-signal platform built on 65nm Bipolar-CMOS-DMOS (BCD) technology.
What you'll do
- Own mixed-signal verification for assigned analog IP blocks using SystemVerilog and UVM-based methodologies.
- Develop scalable digital-on-top testbenches incorporating behavioral models of analog IP.
- Translate analog specifications into executable verification plans, assertions, coverage, and checkers.
- Develop and maintain behavioral models using SystemVerilog real-number modeling.
- Execute regressions, analyze results, and drive debug across analog, digital, and mixed-signal boundaries.
- Verify configuration, calibration, monitoring, and fault-handling interfaces between analog IP and digital logic.
What you'll need
- Bachelor’s or Master’s degree in Electrical Engineering or related field.
- Minimum of 8 years of experience in mixed-signal or digital IC verification.
- Strong proficiency in SystemVerilog and UVM-based verification.
- Hands-on experience building behavioral models using Verilog-A/AMS or SystemVerilog real-number modeling.
- Experience verifying analog IP within digital-on-top SoC environments.
Nice to have
- Familiarity with power management or clocking architectures (BGs, PLLs, LDOs, DC/DCs).
- Experience with coverage-driven verification and assertion-based methodologies.
- Exposure to automotive or industrial silicon reliability and safety requirements.
- Interest in automation, scripting, or AI-assisted verification workflows.
Skills: mixed-signal verification, SystemVerilog, UVM, behavioral modeling, analog IP
This role has been open 27 days — well below the 63-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1169
|
Median days open
63 d
|
Median salary
$188k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | onsemi | All employers we track in this specialty (1169 roles · 95 employers) |
|---|---|---|
| Open roles in this specialty | 15 | 1169 |
| Open roles in the wider Digital Design & Verification family | 57 | 3113 · 115 employers |
| Median days open | 59 d | 63 d (−4 d vs this employer) |
| Median salary (USD postings) | — | $188k |
Skills observed across this category: mixed-signal verification, SystemVerilog, UVM, behavioral modeling, analog IP
Who's hiring in this category
- AMD · 104 open roles · median 39 d
- Qualcomm · 97 open roles · median 53 d
- NVIDIA · 86 open roles · median 70 d
- Synopsys · 62 open roles · median 23 d
- SiFive · 57 open roles · median 56 d
- NXP Semiconductors · 52 open roles · median 76 d
How we counted: 1169 open Design Verification (Design Verification) roles from 95 employers tracked in the SemiconductorJobs index, counted 29 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.