Staff Implementation Engineer - Austin, Texas, United States
$198,100 - $268,000 USD yearly
Originally posted 1 October 2026 by the employer.
About the role
As a Staff Implementation Engineer in Arm's Solutions Engineering group, you will deliver CPU, GPU, interconnect, and SoC designs from RTL through GDSII and tapeout.
What you'll do
- Own and drive end-to-end RTL-to-GDSII physical implementation of processor cores, graphics units, communication fabrics, subsystems, and SoC builds through tapeout. - Collaborate directly with RTL and architecture teams to translate architectural and PPA requirements into implementation targets. - Drive timing closure across MCMM scenarios, including setup, hold, clocking, and complex timing-path analysis. - Own physical implementation readiness and closure across STA, physical verification, power integrity, and tapeout signoff requirements. - Work closely with DFT teams to ensure scan, test modes, and other DFT requirements are correctly implemented and closed. - Debug implementation and EDA-tool issues, and develop automation and flows using Tcl, Python, Perl, shell, or Make.
What you'll need
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field (or equivalent practical experience). - 10+ years of hands-on ASIC physical build and implementation experience, with demonstrated ownership from RTL to GDSII and tapeout. - Hands-on expertise in synthesis, floorplanning, physical partitioning, power delivery network (PDN) planning, placement, clock tree synthesis, and routing. - Solid grasp of MCMM timing closure, timing constraints, clocking, OCV methodologies, crosstalk/SI, and advanced-node timing challenges. - In-depth knowledge of low-power implementation, including UPF, multiple voltage domains, power gating, level shifters, isolation, and voltage/frequency scaling. - Strong scripting and automation skills using Tcl, Python, Perl, shell, and/or Make.
Nice to have
- Experience implementing high-performance Arm CPUs, GPUs, coherent interconnects, or complex SoCs. - Experience with hierarchical physical design and integration of multiple IPs or subsystems. - Experience with structured clock architectures and complex clock-distribution methodologies. - Experience working directly with foundries, EDA vendors, and Physical IP providers on implementation and signoff issues.
Skills: RTL-to-GDSII, synthesis, floorplanning, timing closure, STA, PDN
This role has been open 0 days — well below the 64-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
682
|
Median days open
64 d
|
Median salary
$186k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Arm Holdings | All employers we track in this specialty (682 roles · 81 employers) |
|---|---|---|
| Open roles in this specialty | 19 | 682 |
| Open roles in the wider Physical Implementation family | 43 | 1560 · 112 employers |
| Median days open | 0 d | 64 d (−64 d vs this employer) |
| Median salary (USD postings) | — | $186k |
Skills observed across this category: RTL-to-GDSII, synthesis, floorplanning, timing closure, STA, PDN
Who's hiring in this category
- Qualcomm · 121 open roles · median 49 d
- AMD · 63 open roles · median 32 d
- Intel Corporation · 38 open roles · median 20 d
- Synopsys · 38 open roles · median 42 d
- Broadcom · 37 open roles · median 98 d
- NVIDIA · 36 open roles · median 68 d
How we counted: 682 open Physical Design (Physical Design) roles from 81 employers tracked in the SemiconductorJobs index, counted 28 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.