Staff Hardware Test & Bring-Up Engineer - Mountain View, CA, United States
$187,000 USD yearly
Originally posted 16 July 2026 by the employer. Relisted by the employer on 24 September 2026.
Lead hardware bring-up and automated system-level testing for photonic ICs mounted on system-level evaluation boards.
About the role
The Staff Hardware Test & Bring-Up Engineer leads the development of automated system-level tests from hardware bring-up through mass production ramp. The role focuses on electrical bring-up and test execution for photonic ICs mounted on system-level evaluation boards.
What you'll do
- Lead end-to-end hardware bring-up for ATE HW and partner directly with equipment suppliers to debug hardware anomalies. - Lead initial electrical bring-up for photonic ICs products mounted on system-level evaluation boards. - Architect and build robust, automated system-level test software programs in Python or C/C++ running on the test bench. - Collaborate with IC Design, DFT, and Firmware teams to define hardware test requirements and isolate silicon versus board-level bugs.
What you'll need
- Bachelor’s in Electrical Engineering, Computer Engineering, or a related technical discipline with 8+ years of hands-on experience in physical hardware bring-up, PCBA functional testing, and custom ATE loadboard/socket integration for complex ASICs/SoCs. - Expertise in validating complex multi-rail power-up/power-down sequences and troubleshooting dynamic load behaviors. - Deep practical mastery of JTAG, QSPI/QPI, I2C, and SPI communication protocols. - Experience driving hardware verification, integrating firmware diagnostic APIs, and executing direct register read/write routines. - Advanced proficiency in Python or C/C++ for writing test executives, automating sequences over hardware bridges, and programmatic control of lab instrumentation. - Expert hands-on command of standard bench equipment: digital multimeters (DMMs), Source Measure Units (SMUs), programmable power supplies, oscilloscopes, and logic analyzers.
Nice to have
- Master’s degree with 6+ years of industry experience. - Experience with embedded microcontrollers or debugging low-level firmware drivers. - Familiarity with boundary scan (BSDL) tools, DFT concepts (MBIST, Scan), or standard ATE architectures. - Basic understanding of eFUSE programming circuits, ADC/DAC calibration routines, or precision thermal sensing.
This role has been open 96 days — well above the 33-day median for Silicon Test Engineering roles.
Silicon Test Engineering · DFT Test
|
Open roles in category
556
|
Median days open
33 d
|
Median salary
$173k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Lightmatter | All employers we track in this specialty (556 roles · 77 employers) |
|---|---|---|
| Open roles in this specialty | 5 | 556 |
| Open roles in the wider Silicon Validation & Test family | 9 | 2242 · 113 employers |
| Median days open | 36 d | 33 d (+3 d vs this employer) |
| Median salary (USD postings) | — | $173k |
Who's hiring in this category
- Teradyne · 79 open roles · median 27 d
- Renesas Electronics · 44 open roles · median 27 d
- Infineon Technologies · 43 open roles · median 41 d
- Micron Technology · 28 open roles · median 37 d
- Qualcomm · 28 open roles · median 33 d
- Texas Instruments · 24 open roles · median 28 d
How we counted: 556 open Silicon Test Engineering (DFT Test) roles from 77 employers tracked in the SemiconductorJobs index, counted 21 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.