Staff Engineer, SRAM Circuit Design - San Jose, California, United States

Originally posted 16 September 2026 by the employer. Relisted by the employer on 15 October 2026.

This role involves leading the development of SRAM memory arrays, including bit cells, sense amplifiers, decoders, and control circuits for advanced process nodes.

About the role

As a Staff Engineer, SRAM Circuit Design, you will lead the development of SRAM solutions. This role drives the end-to-end design of high-performance, low-power memory circuits used in semiconductor products, influencing the power, performance, and area (PPA) efficiency of future computing, mobile, and AI platforms.

What you'll do

• Design and develop SRAM memory arrays, including bit cells, sense amplifiers, decoders and control circuits for advanced process nodes (e.g., 2nm, 3nm and 5nm).
• Optimize SRAM designs for performance, power, area (PPA), and yield.
• Develop custom layouts and perform physical design verifications (e.g., DRC, LVS).
• Evaluate trade-offs between speed, power, and area to meet design targets.
• Develop and improve SRAM design methodologies, including automation scripts for design, simulation, and verification.
• Perform extensive circuit simulations using tools like HSPICE, Finesim, or Cadence Spectre to validate SRAM functionality and performance.

What you'll need

• Bachelor's degree in electrical engineering with 10+ years of industry experience or master's degree in electrical engineering with 8+ years of experience.
• Prior experience in SRAM or memory circuit design, with a proven track record of delivering SRAM designs in advanced process nodes.
• Strong understanding of semiconductor device physics and process technology (FinFET, GAA, SOI, etc.).
• Expertise in SRAM architecture, including bitcells, sense amplifiers, write drivers, and read/write control paths.
• Proficiency in circuit simulation, variation analysis, and design tools such as Spectre, HSPICE, Cadence Virtuoso, etc.
• Knowledge of scripting languages (e.g., Python, Perl, TCL) for automation of design tasks.
• Experience with advanced technology nodes (e.g., 5nm, 3nm, or beyond).

Nice to have

• Familiarity with timing analysis, power analysis, and design for manufacturability (DFM).
• Knowledge of SRAM compiler development and experience with low-power SRAM design techniques (e.g., power gating, voltage scaling).
• Background in silicon debug and root-cause analysis.

Skills: SRAM circuit design, bit cells, sense amplifiers, decoders, advanced process nodes