Originally posted 22 September 2026 by the employer.
About the role
This role involves driving power-efficient architectures for SoCs, focusing on optimizing dynamic power, Vmin reduction, and leakage power.
What you'll do
- Explore and optimize SoC-level power architecture features and their dependencies with IP blocks.
- Conduct energy and latency sensitivity studies of dynamic power reduction techniques like DVFS, clock gating, power gating, and micro/macro power collapse.
- Analyze and optimize Vmin margins, power-performance tradeoffs, and silicon robustness.
- Drive leakage reduction and low-power design techniques across advanced process nodes.
- Evaluate efficient techniques for managing voltage droops, overshoots, thermal, and electrical limits.
- Develop MATLAB models to quantify PPA KPIs of power architecture features and use SPICE simulations to optimize SoC/System-level architecture.
What you'll need
- Bachelor's/Master's degree in Electrical/Electronics Engineering or a related field.
- 8 years of experience in SoC Power Architecture, Energy Management, and Low-Power Design.
- Strong expertise in Dynamic Power Optimization.
- Strong expertise in Vmin Analysis and Margining.
- Strong expertise in Leakage Power Reduction.
- Strong expertise in Low-Power Design Techniques.
- Strong expertise in PDN/Power Integrity Analysis.
- Strong expertise in DVFS, Clock Gating, Power Gating.
- Hands-on experience with MATLAB Modeling.
- Hands-on experience with SPICE Simulations.
- Hands-on experience with Lab power/perf data crunching.
Skills: SoC Power Architecture, dynamic power optimization, Vmin reduction, leakage power, DVFS, power gating
More semiconductor jobs: Qualcomm jobs · SoC design jobs · India jobs
This role has been open 44 days — well below the 77-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
492
|
Median days open
77 d
|
Category median salary (all employers)
$230k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (492 roles · 68 employers) |
|---|---|---|
| Open roles in this specialty | 80 | 492 |
| Open roles in the wider Digital Design & Verification family | 403 | 3497 · 120 employers |
| Median days open | 88 d | 77 d (+11 d vs this employer) |
| Median salary (USD postings) | — | $230k |
Skills observed across this category: SoC Power Architecture, dynamic power optimization, Vmin reduction, leakage power, DVFS, power gating
Who's hiring in this category
- Qualcomm (this employer) · 79 open roles · median 90 d
- NVIDIA · 63 open roles · median 78 d
- Apple · 39 open roles · median 16 d
- AMD · 37 open roles · median 71 d
- Arm Holdings · 28 open roles · median 8 d
- Micron Technology · 20 open roles · median 89 d
How we counted: 492 open SoC/Chip Architecture (SOC Architecture) roles from 68 employers tracked in the SemiconductorJobs index, counted 5 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.