Staff Engineer, Memory Systems Architecture - San Jose, California, United States

Originally posted 20 March 2026 by the employer.

About the role

As a Staff Engineer, Memory Systems Architecture on the Fault Management team, you will identify DRAM failure modes, abnormalities, and failure rate projections using field failure telemetry data. You will analyze memory fleet telemetry to enable virtual root-cause analysis and minimize system downtime across hardware deployments.

What you'll do

- Leverage knowledge of SOC controllers and memory operations, including RAS features, to recommend solutions that mitigate field DRAM failure rates. - Communicate ECC schemes to customers based on Samsung DRAM DQ and burst failure modes. - Interface with customers to establish the value add of enabling in-field fault management architecture. - Contribute to the standardization of DRAM/HBM failure logging within the Open Compute Project (OCP). - Propose and develop platform RAS algorithms for memory fault management, including page offlining and hPPR, and conduct POCs with known failure DIMMs in real servers and applications.

What you'll need

- Bachelor’s degree with 10+ years of relevant industry experience, Master’s degree with 8+ years, or PhD with 5+ years in hardware fault management, reliability, or data center fleet management. - Knowledge of platform memory subsystems and platform RAS mechanisms, including ECC, page offlining, hPPR, and hardware sparing. - Experience with ECC design, verification, and reverse engineering. - Understanding of address mapping between CPU and memory. - Experience with memory controller register modification. - Linux kernel commit experience and an understanding of DRAM and HBM failure modes.

Skills: Memory Systems Architecture, DRAM failure analysis, fault management, AI/ML hardware deployments, memory fleet telemetry, virtual root-cause analysis