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Synopsys

Staff Engineer - Memory Design

Synopsys img src="https://tbcdn.talentbrew.com/company/44408/gst_v1/img/icon-map-black.png" height="15" width="15" alt="pin icon">Bengaluru, India 2 months ago
Digital Design & SoC Architecture

Originally posted 16 August 2026 by the employer.

About the role

This role involves designing and developing embedded CMOS memories for Synopsys IP products. You will own memory blocks from architecture through tapeout, working with compiler teams and reviewing layouts.

What you'll do

  • Design and develop embedded CMOS memories including single-port SRAM, dual-port SRAM, register files, and ROM.
  • Own circuit architecture and transistor-level implementation for ultra-high-speed, ultra-low-power, or high-density memory configurations.
  • Perform schematic entry, SPICE simulation, layout planning, and supervise physical layout execution through to final verification.
  • Develop and verify bitcells, define layout rules, and drive layout design and parasitic extraction closure with the physical design team.
  • Interface with CAD teams to integrate memory designs into compiler automation flows and generate EDA models.
  • Mentor junior engineers and lead technical aspects of memory design projects from concept to delivery.

What you'll need

  • Bachelor's or Master's degree in Electrical Engineering, Electronics, or a related technical field.
  • Deep hands-on experience with CMOS memory circuit design including SRAM, register files, or ROM.
  • Proficiency with circuit simulation tools such as HSPICE, Spectre, or similar SPICE-based simulators.
  • Strong understanding of memory layout design, parasitic extraction, and layout verification tools like Calibre or Assura.
  • Scripting capability in C-Shell, Perl, or similar languages.
  • Demonstrated ability to lead technical projects and mentor junior engineers.

Nice to have

  • Experience with C++ or JavaScript.
  • Experience working with memory compiler flows, EDA model generation, or design automation.

Skills: memory circuits, SRAM, register files, bitcells, SPICE simulation, layout design

Market context

This role has been open 48 days — well below the 69-day median for Memory Design roles.

Memory Design · Memory Design

Open roles in category
287
Median days open
69 d
Median salary
$205k
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
How Synopsys compares in Memory Design hiring
Metric Synopsys All employers we track in this specialty (287 roles · 29 employers)
Open roles in this specialty 27 287
Median days open 49 d 69 d (−20 d vs this employer)
Median salary (USD postings) — $205k

Skills observed across this category: memory circuits, SRAM, register files, bitcells, SPICE simulation, layout design

Who's hiring in this category

  • Micron Technology · 151 open roles · median 86 d
  • Synopsys (this employer) · 27 open roles · median 49 d
  • SanDisk · 17 open roles · median 32 d
  • Broadcom · 16 open roles · median 50 d
  • Qualcomm · 12 open roles · median 149 d
  • NVIDIA · 7 open roles · median 59 d

How we counted: 287 open Memory Design (Memory Design) roles from 29 employers tracked in the SemiconductorJobs index, counted 5 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.

Synopsys

Synopsys

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img src="https://tbcdn.talentbrew.com/company/44408/gst_v1/img/icon-map-black.png" height="15" width="15" alt="pin icon">Bengaluru, India
On-site
2 months ago

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