Staff Engineer, IP Dev Layout - Hyderabad - Phoenix Aquila, India
Originally posted 19 August 2026 by the employer.
Develop IP layouts for Memory designs.
About the role
This role is responsible for the design and development of critical analog, mixed-signal, and custom digital block layouts, including full chip level integration support. The position specifically involves work on Memory designs.
What you'll do
- Design and develop critical analog, mixed-signal, custom digital block layouts.
- Provide full chip level integration support.
- Perform layout verification including LVS, DRC, and Antenna checks.
- Ensure on-time delivery of block-level layouts with acceptable quality.
- Lead planning, area/time estimation, scheduling, and execution for project timelines.
- Communicate effectively with global engineering teams to ensure layout project success.
What you'll need
- 8 to 15 years' experience in analog/custom layout in advanced CMOS process.
- Experience in various technology nodes including Planar and FinFET.
- Expertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS.
- Hands-on experience in creating layouts of critical blocks such as Temperature sensor, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, and Differential Amplifier.
- Good understanding of Analog Layout fundamentals (e.g., Matching, Electro-migration, Latch-up, coupling, crosstalk, IR-drop, active and passive static device parasitics).
- Understanding layout effects on circuit characteristics such as speed, capacitance, power, and area.
Skills: analog/custom layout, FinFET, Cadence VLE/VXL, DRC/LVS, Memory designs
This role has been open 41 days — well above the 25-day median for Analog IC Design roles.
Analog IC Design · Analog Layout
|
Open roles in category
49
|
Median days open
25 d
|
Median salary
—
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (49 roles · 21 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 49 |
| Open roles in the wider Analog & Mixed-Signal family | 48 | 1385 · 107 employers |
| Median days open | 41 d | 25 d (+16 d vs this employer) |
| Median salary (USD postings) | — | — |
Skills observed across this category: analog/custom layout, FinFET, Cadence VLE/VXL, DRC/LVS, Memory designs
Who's hiring in this category
- Celero · 8 open roles · median 32 d
- Analog Devices · 7 open roles · median 12 d
- Marvell Technology · 4 open roles · median 16 d
- Broadcom · 3 open roles · median 8 d
- onsemi · 3 open roles · median 35 d
- QORVO · 3 open roles · median 33 d
How we counted: 49 open Analog IC Design (Analog Layout) roles from 21 employers tracked in the SemiconductorJobs index, counted 30 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.