Staff Engineer, High-Speed I/O Analog-Mixed Circuit - San Jose, California, United States
$163,000 - $253,000 USD yearly
Originally posted 29 January 2026 by the employer.
Design high-speed memory interface circuits spanning DDR, LPDDR, GDDR, and HBM I/O architectures.
About the role
As a Staff Engineer in the Memory IO Lab, you will design and verify analog and mixed-signal circuits for memory interface technologies. The role focuses on developing memory interface solutions adopted in DDR, LPDDR, GDDR, and HBM I/O interfaces.
What you'll do
- Execute hands-on analog circuit design, run simulations to confirm functionality and performance, and partner with the verification team on mixed-signal designs including high-speed data converters, PLL, and SERDES. - Own circuit and system specifications and document designs alongside simulation results using CAD tools. - Guide layout floor-planning at block and top levels, supervise layout activities, provide concise guidelines to layout engineers, and draw layout hands-on when necessary. - Work closely with device and process teams to define transistor specifications. - Support silicon bring-up and automated measurement using scripts.
What you'll need
- BS with 10+ years of experience, MS with 8+ years of experience, or PhD with 5+ years of experience in Electrical Engineering or Computer Science. - 5+ years of experience working with system on chip architecture, high-speed serial interfaces, and analog mixed-signal circuit design using advanced CMOS technology nodes. - Direct design experience with high-speed interface standards such as DDR, LPDDR, GDDR, or HBM I/O. - Detailed technical knowledge of high-speed I/O design components, including DLL, PLL, FFE, CTLE, DFE, output drivers, ODT, Duty Cycle Correction (DCC), training/calibration, and both high-speed and low-power power design. - Practical experience in high-frequency clock distribution design, implementation, and analysis, as well as layout requirements of high-speed circuits. - Proficiency with EDA tools such as Cadence, MATLAB (Simulink), and EM tools, combined with scripting and automation skills using Tcl or Perl.
Nice to have
- Knowledge of Python.
Skills: SerDes, High-Speed I/O, DDR, PLL, CTLE, DFE
This role has been open 0 days — well below the 72-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
234
|
Median days open
72 d
|
Median salary
$177k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Samsung Semiconductor | All employers we track in this specialty (234 roles · 46 employers) |
|---|---|---|
| Open roles in this specialty | 6 | 234 |
| Open roles in the wider Analog & Mixed-Signal family | 10 | 1428 · 107 employers |
| Median days open | 83 d | 72 d (+11 d vs this employer) |
| Median salary (USD postings) | — | $177k |
Skills observed across this category: SerDes, High-Speed I/O, DDR, PLL, CTLE, DFE
Who's hiring in this category
- Synopsys · 31 open roles · median 36 d
- AMD · 26 open roles · median 40 d
- Qualcomm · 20 open roles · median 63 d
- Cadence Design Systems · 19 open roles · median 155 d
- Micron Technology · 15 open roles · median 36 d
- Apple · 12 open roles · median 22 d
How we counted: 234 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 46 employers tracked in the SemiconductorJobs index, counted 21 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.