Staff Engineer Formal(IOMMU-N) - Bengaluru, Karnataka, India
Originally posted 16 September 2026 by the employer — open 1 day.
About the role
This role involves developing and implementing formal verification plans for complex digital designs, primarily targeting RISC-V processors and other IP blocks designed in Chisel.
What you'll do
- Develop and implement formal verification plans for complex digital designs, primarily targeting RISC-V processors and other IP blocks designed in Chisel.
- Write and debug formal properties (assertions and assumptions) in Chisel/Scala to specify design behavior and identify corner-case bugs.
- Utilize formal verification tools to prove design correctness and uncover potential issues.
- Develop verification environments and infrastructure using Chisel, Scala, and TCL scripting.
- Identify and implement strategies for improving formal verification efficiency and coverage, including functional coverage and constrained-random verification techniques seen in methodologies like UVM adapted for Chisel.
- Analyze formal verification results, debug failures, and work with the design team to resolve issues.
What you'll need
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
- 7+ years of hands-on experience in formal verification of digital hardware designs.
- Proficiency in Scala programming, with hands-on experience in Chisel hardware description language.
- Strong understanding of formal verification methodologies (e.g., assertion-based verification, model checking, equivalence checking).
- Experience in writing effective formal properties and assertions.
- Familiarity with formal verification tools and their application.
- Experience with TCL scripting for tool automation and flow development.
- Solid understanding of digital design principles, computer architecture, and FPGA/ASIC design flows.
Skills: formal verification plans, digital designs, RISC-V processors, Chisel/Scala, formal properties
This role has been open 1 day — well below the 56-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1122
|
Median days open
56 d
|
Median salary
$192k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | SiFive | All employers we track in this specialty (1122 roles · 92 employers) |
|---|---|---|
| Open roles in this specialty | 51 | 1122 |
| Open roles in the wider Digital Design & Verification family | 82 | 3007 · 114 employers |
| Median days open | 44 d | 56 d (−12 d vs this employer) |
| Median salary (USD postings) | — | $192k |
Skills observed across this category: formal verification plans, digital designs, RISC-V processors, Chisel/Scala, formal properties
Who's hiring in this category
- Qualcomm · 104 open roles · median 53 d
- AMD · 99 open roles · median 33 d
- NVIDIA · 90 open roles · median 65 d
- Micron Technology · 56 open roles · median 96 d
- Synopsys · 54 open roles · median 23 d
- SiFive (this employer) · 51 open roles · median 44 d
How we counted: 1122 open Design Verification (Design Verification) roles from 92 employers tracked in the SemiconductorJobs index, counted 17 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.