Staff Engineer Digital Signal Processing - San Jose
$125,680 - $172,810 USD yearly
Originally posted 2 March 2026 by the employer — open 191 days.
Focus on Automotive Ethernet/SerDes research and development.
About the role
This role involves Digital Signal Processing on the Research & Development team.
What you'll do
- Conduct Automotive Ethernet/SerDes research and development with design and simulation.
- Provide DSP specification and RTL validation support.
- Build channel models and simulation platforms in MATLAB or C.
- Perform transceiver block design and performance evaluations based on simulations.
- Support DSP chip bring-up, lab data collection, and chip debugging for RMAs.
What you'll need
- EE Ph.D. with 0-1 years of experience or Master's degree with 1-3 years of work experience.
- Knowledge of Digital Signal Processing.
- Knowledge of Digital Communication Theory.
- Knowledge of Transmission Line Theory.
- Basic knowledge of Digital Design.
- Familiarity with MATLAB.
- Familiarity with C++ languages.
Nice to have
- Basic knowledge of Analog Design.
- Basic knowledge of Electro-Magnetic Compliance.
- Basic knowledge of Forward Error Correction theory.
- RTL coding experience.
Skills: Digital Signal Processing, Digital Communication Theory, Transmission Line Theory, Automotive Ethernet/SerDes, channel model, transceiver block design
This role has been open 154 days — well above the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Infineon Technologies | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in category | 5 | 217 |
| Median days open | 76 d | 91 d (−15 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: Digital Signal Processing, Digital Communication Theory, Transmission Line Theory, Automotive Ethernet/SerDes, channel model, transceiver block design
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Figures refresh nightly.