Staff Engineer- DFT
Focus on DFT methodology and flow for optical DSP ASICs developed in TSMC advanced process nodes.
Originally posted 5 November 2026 by the employer.
About the role
Marvell is seeking a Staff DFT Engineer in Santa Clara to set up the methodology and flow for optical DSP (ODSP) ASICs. The role supports products including multi-terabit retimers, coherent DSP devices, and high-speed optical transceivers developed in TSMC advanced process nodes.
What you'll do
- Implement scan, compression, OCC, wrappers, and MBIST on assigned blocks and partitions.
- Run ATPG, analyze coverage, and drive coverage improvement through test points and fault exclusions.
- Run DFT DRC, gate-level (zero-delay and SDF) simulations, and debug failures.
- Support DFT timing constraints and closure with physical design and STA teams.
- Generate patterns and support silicon bring-up and ATE pattern debug.
- Write scripts for flow automation and document methodology.
What you'll need
- BS in EE/CE with 5+ years of DFT experience, or MS in EE/CE with 3+ years of experience.
- Hands-on experience with scan, ATPG, MBIST, and JTAG using Synopsys or Siemens tools.
- Proficiency in Verilog or SystemVerilog, and scripting experience with Tcl, Python, or Perl.
- Understanding of ASIC flow, STA, and gate-level simulation.
More semiconductor jobs: Marvell Technology jobs · DFT engineer jobs · Santa Clara jobs
This role has been open 0 days — well below the 55-day median for DFT Engineering roles.
DFT Engineering · DFT Test
|
Open roles in category
279
|
Median days open
55 d
|
Category median salary (all employers)
$206k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Marvell Technology | All employers we track in this specialty (279 roles · 55 employers) |
|---|---|---|
| Open roles in this specialty | 7 | 279 |
| Open roles in the wider Digital Design & Verification family | 41 | 3488 · 119 employers |
| Median days open | 8 d | 55 d (−47 d vs this employer) |
| Median salary (USD postings) | — | $206k |
Who's hiring in this category
- AMD · 37 open roles · median 54 d
- NVIDIA · 23 open roles · median 54 d
- Qualcomm · 22 open roles · median 84 d
- Broadcom · 21 open roles · median 2 d
- NXP Semiconductors · 20 open roles · median 54 d
- Synopsys · 19 open roles · median 34 d
How we counted: 279 open DFT Engineering (DFT Test) roles from 55 employers tracked in the SemiconductorJobs index, counted 5 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.