Staff Engineer, Design Verification Engineering - AZ, Chandler, East Elliot, United States
$172,390 - $199,229 USD yearly
Originally posted 12 May 2026 by the employer.
About the role
Define and verify interfaces, state machines, and controlling logic required to implement new products for Data Center, Energy, and Automotive applications. The role spans metric-driven SystemVerilog and UVM verification environments alongside mixed-signal simulation using Cadence AMS.
What you'll do
- Architect, implement, and manage complete metric-driven SystemVerilog and UVM verification environments based on project complexity. - Develop directed and constrained random test cases in SystemVerilog, including SystemVerilog Assertions for dynamic and formal verification. - Design and maintain mixed-signal simulations using Cadence AMS, writing Verilog-AMS and Real Number Models. - Define and verify interfaces, state machines, and controlling logic for Data Center, Energy, and Automotive products. - Participate in product definition, verification test plan creation, regression suite development, and coverage closure.
What you'll need
- Master’s degree in Electrical Engineering, Materials Engineering, Physics, or related discipline with 4 years of experience, or a Bachelor’s degree with 6 years of experience in module-level design with Verilog RTL and functional verification. - Demonstrated expertise with mixed-signal IC verification techniques using SystemVerilog and UVM, test plan creation, coverage closure, and regression suites. - Experience defining, designing, and verifying custom state machines and control logic for analog and mixed-signal circuits, including data converters, linear regulators, high-speed serial interfaces, and microcontrollers. - Experience defining and implementing custom digital interfaces including I2C, SPI, and UART. - Experience with logic synthesis with timing and placement constraints, timing and power analysis, logic equivalence checking, design for test, scan insertion, and ATPG. - Hands-on proficiency with verification tools (Xcelium or VCS) and scripting languages (Perl, Python, and C).
Skills: SystemVerilog, UVM, mixed-signal simulation, Verilog-AMS, AMS, functional verification
This role has been open 173 days — well above the 65-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1259
|
Median days open
65 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Analog Devices | All employers we track in this specialty (1259 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 41 | 1259 |
| Open roles in the wider Digital Design & Verification family | 99 | 3328 · 115 employers |
| Median days open | 60 d | 65 d (−5 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: SystemVerilog, UVM, mixed-signal simulation, Verilog-AMS, AMS, functional verification
Who's hiring in this category
- Qualcomm · 120 open roles · median 44 d
- NVIDIA · 93 open roles · median 65 d
- AMD · 92 open roles · median 54 d
- Synopsys · 65 open roles · median 40 d
- SiFive · 55 open roles · median 82 d
- Cadence Design Systems · 52 open roles · median 124 d
How we counted: 1259 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 25 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.