Staff Engineer, Compiler - San Jose, California, United States
$163,000 - $253,000 USD yearly
Originally posted 2 June 2026 by the employer.
Build and lower kernel DSLs to custom hardware backends within Samsung Semiconductor's AGI Computing Lab.
About the role
This role joins the AGI Computing Lab to solve system-level compiler challenges for AI/ML workloads across memory, computing, and interconnect architectures. You will lower high-level compiler IRs and kernel DSLs to custom hardware backends and non-uniform memory hierarchies.
What you'll do
- Adapt torch.compile to custom hardware backends by lowering Inductor's IR, defining fusion, specialization, and transitions to hand-written kernels. - Build or extend kernel DSLs (such as Triton or Helion styles) and lower them to custom ISAs, memory hierarchies, and collective primitives. - Design graph placement and scheduling passes across distributed memory models to overlap compute with data movement. - Implement parallelism-aware lowering in compiler IR for tensor, pipeline, expert, and sequence parallelism. - Resolve fusion, tiling, and memory planning constraints for non-uniform memory hierarchies. - Drive upstream open-source contributions and reviews for PyTorch, Triton, Helion, and related projects.
What you'll need
- Bachelor’s with 10+ years, Master’s with 8+ years, or PhD with 5+ years of industry experience. - 3-5+ years of industry experience in at least one of: Triton, Helion, MLIR, XLA, TVM, Inductor, IREE, CUTLASS, or a proprietary equivalent. - Experience designing a kernel DSL or its IR from scratch, or making non-trivial language-level changes to an existing one. - Experience with MLIR, including writing dialects, passes, or backend integration. - Experience building PyTorch backends for non-CUDA accelerators (XPU, ROCm, MPS, TPU, or custom). - Experience with kernel autotuning, performance modeling, or cost-based compilation. - Background in HPC, distributed systems, or NUMA-aware programming for non-flat memory architectures.
Skills: compiler, AI/ML workloads, hardware accelerators, PyTorch, Triton, MLIR
This role has been open 142 days — well above the 55-day median for Infrastructure/Platform Software roles.
Infrastructure/Platform Software · GPU Software Stack
|
Open roles in category
242
|
Median days open
55 d
|
Median salary
$220k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Samsung Semiconductor | All employers we track in this specialty (242 roles · 20 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 242 |
| Open roles in the wider Software, Firmware & Systems family | 12 | 6297 · 144 employers |
| Median days open | 142 d | 55 d (+87 d vs this employer) |
| Median salary (USD postings) | — | $220k |
Skills observed across this category: compiler, AI/ML workloads, hardware accelerators, PyTorch, Triton, MLIR
Who's hiring in this category
- NVIDIA · 120 open roles · median 57 d
- AMD · 52 open roles · median 53 d
- Intel Corporation · 25 open roles · median 14 d
- Qualcomm · 18 open roles · median 128 d
- Arm Holdings · 5 open roles · median 121 d
- Graphcore · 4 open roles · median 3 d
How we counted: 242 open Infrastructure/Platform Software (GPU Software Stack) roles from 20 employers tracked in the SemiconductorJobs index, counted 24 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Software, Firmware & Systems family row. Figures refresh nightly.
Samsung Semiconductor
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