Staff ENGINEER - CE CAD - Richardson, TX, United States
Originally posted 15 May 2026 by the employer.
Develop and support physical verification tools, rule decks, and flows for CMOS design and memory development.
About the role
As a CAD Engineer on the EDA and Design Enablement team, you will develop, improve, and support verification tools, rule decks, and flows across the design ecosystem.
What you'll do
- Develop and improve physical verification tools, rule decks, and methodologies for CMOS design, including DRC, LVS, DFM, and PERC. - Debug, evaluate, and support in-house and commercial EDA verification solutions in a production environment. - Develop and maintain rule decks, and guide design teams on physical verification requirements and best practices. - Collaborate closely with design, layout, modeling, and process teams to solve verification and workflow challenges. - Evaluate EDA industry tools to identify opportunities to improve quality, performance, and efficiency. - Document processes and provide training and support for end users.
What you'll need
- Bachelor’s degree in Computer Engineering, Computer Science, or a related field. - 2+ years of experience in CAD, VLSI, or a related semiconductor engineering role. - Experience programming in SVRF/TVF (Calibre), Python, and/or Perl. - Experience with physical verification rule deck development and/or validation, and familiarity with Calibre EDA tools and flows. - Experience working in Linux/Unix environments, shell scripting, databases, and version control.
Nice to have
- Understanding of CMOS process fundamentals and layout design rules. - Experience developing and debugging DRC/LVS rule decks, including antenna, ESD, LUP, and reliability checks. - Experience with parasitic extraction flows and methodologies. - Understanding of physical verification methodologies, flows, and quality metrics.
Skills: Physical Verification tools, DRC/DFM/LVS/PERC, CMOS circuit design, layout automation, SKILL, Python
This role has been open 222 days — well above the 70-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
704
|
Median days open
70 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (704 roles · 74 employers) |
|---|---|---|
| Open roles in this specialty | 45 | 704 |
| Open roles in the wider Physical Implementation family | 77 | 1513 · 111 employers |
| Median days open | 55 d | 70 d (−15 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: Physical Verification tools, DRC/DFM/LVS/PERC, CMOS circuit design, layout automation, SKILL, Python
Who's hiring in this category
- Cadence Design Systems · 156 open roles · median 153 d
- Synopsys · 63 open roles · median 45 d
- Micron Technology (this employer) · 45 open roles · median 55 d
- GlobalFoundries · 40 open roles · median 28 d
- Qualcomm · 39 open roles · median 78 d
- Keysight Technologies · 35 open roles · median 60 d
How we counted: 704 open EDA/CAD Engineering (EDA Tools) roles from 74 employers tracked in the SemiconductorJobs index, counted 27 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.