Staff Engineer, Architecture & Performance Research Engineer for Data Center and Agentic AI CPU
$163,000 - $253,000 USD yearly
Originally posted 26 August 2026 by the employer.
Focus on RISC-V CPU microarchitecture and performance for data center and agentic AI workloads.
About the role
What you'll do
- Propose new architecture ideas and own microarchitectural domains including front-end, mid-end, and back-end.
- Implement architectural ideas using AI-driven design methodologies and validate them on silicon.
- Build, extend, and validate performance models and architectural simulators.
- Perform CPI/IPC analysis and identify root causes of performance bottlenecks.
- Evaluate microarchitectural features and optimizations using trace-driven, analytical, and cycle-accurate models.
- Characterize workloads and benchmarks, including SPEC, server, client, AI/ML, agentic AI, and internal traces.
What you'll need
- Master’s degree in Computer Engineering, Computer Science, or a related field with 8+ years of relevant experience, or PhD with 5+ years of relevant experience.
- 4+ years of experience in CPU microarchitecture or performance engineering.
- Experience designing RISC-V, ARM, x86 CPU cores, or GPU/NPU vector unit.
- Strong understanding of out-of-order execution, branch prediction, pipelines, speculation, and cache/memory systems.
- Hands-on experience with architectural simulators such as gem5.
- Proficiency in C/C++ and Python.
- Experience analyzing large-scale performance data and traces.
Nice to have
- Experience with AI-driven or agentic design workflows, including high-level design languages and AI-assisted RTL generation.
- Understanding of agentic AI workload execution patterns.
- Domain-specific experience in Front-end: Branch prediction and decoupled fetch, particularly for compiler- or interpreter-driven workloads.
- Domain-specific experience in Mid-end: RVV/SIMD, matrix/tensor engine design, and out-of-order vector execution.
- Domain-specific experience in Back-end: LSU/MSHR design and prefetcher design for irregular access patterns.
- Experience with PPA trade-off analysis.
- Experience with CPU tapeout or silicon validation.
- Experience with patents or technical publications.
Skills: CPU architectures, microarchitectural innovation, performance models, AI-driven methodologies, silicon validation
This role has been open 50 days — well below the 79-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
470
|
Median days open
79 d
|
Median salary
$235k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Samsung Semiconductor | All employers we track in this specialty (470 roles · 65 employers) |
|---|---|---|
| Open roles in this specialty | 6 | 470 |
| Open roles in the wider Digital Design & Verification family | 13 | 3183 · 115 employers |
| Median days open | 46 d | 79 d (−33 d vs this employer) |
| Median salary (USD postings) | — | $235k |
Skills observed across this category: CPU architectures, microarchitectural innovation, performance models, AI-driven methodologies, silicon validation
Who's hiring in this category
- Qualcomm · 72 open roles · median 86 d
- NVIDIA · 56 open roles · median 68 d
- Apple · 39 open roles · median 9 d
- AMD · 35 open roles · median 64 d
- Arm Holdings · 27 open roles · median 112 d
- NXP Semiconductors · 21 open roles · median 114 d
How we counted: 470 open SoC/Chip Architecture (SOC Architecture) roles from 65 employers tracked in the SemiconductorJobs index, counted 15 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.
Samsung Semiconductor
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