Staff Engineer - Analog Design
Originally posted 25 August 2026 by the employer.
About the role
This role involves designing and micro-architecting analog and IO circuits, including GPIOs, I3C, and SD-eMMC PHY, for advanced technology nodes from 2nm GAA to 55nm bulk.
What you'll do
- Design and micro-architect analog and IO circuits from specifications, including GPIOs, I2C, I3C, SD-eMMC PHY, SPI, SPMI, RGMII, ONFI, RFFE, I2S, UART, and SMBUS blocks.
- Develop circuit topologies that meet PPA targets across advanced technology nodes including sub-2nm GAA, GAE, FinFET, FDSOI, and bulk processes.
- Perform detailed network analysis, transistor-level simulations, and corner analysis to validate design performance and reliability.
- Conduct design reliability analysis including ESD, latch-up, aging, and stress testing to meet automotive, space, and industrial standards.
- Collaborate with layout teams to ensure designs are optimized for area, parasitic effects, and manufacturability.
- Work with foundry PDKs to ensure designs are aligned with process capabilities and constraints across all top foundries.
What you'll need
- Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, or equivalent technical field.
- 2 to 6 years of hands-on experience in analog circuit design, IO design, or mixed-signal design.
- Deep understanding of analog circuit design techniques including amplifiers, references, regulators, comparators, and interface circuits.
- Strong grasp of semiconductor device physics and how transistor-level behavior impacts circuit performance across process nodes.
- Proficiency in network analysis and ability to apply it to real-world circuit design problems.
- Good grip on design reliability analysis including ESD, latch-up, aging, and stress effects.
- Experience with circuit simulation tools such as HSPICE, Spectre, or similar SPICE-based environments.
Skills: analog and IO circuits, GPIOs, I3C, MIPI, SD-eMMC PHY, transistor-level simulations, ESD, latch-up
This role has been open 34 days — well below the 65-day median for Analog IC Design roles.
Analog IC Design · Analog Design
|
Open roles in category
282
|
Median days open
65 d
|
Median salary
$153k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Synopsys | All employers we track in this specialty (282 roles · 51 employers) |
|---|---|---|
| Open roles in this specialty | 4 | 282 |
| Open roles in the wider Analog & Mixed-Signal family | 36 | 1385 · 107 employers |
| Median days open | 31 d | 65 d (−34 d vs this employer) |
| Median salary (USD postings) | — | $153k |
Skills observed across this category: analog and IO circuits, GPIOs, I3C, MIPI, SD-eMMC PHY, transistor-level simulations
Who's hiring in this category
- Texas Instruments · 33 open roles · median 76 d
- Micron Technology · 27 open roles · median 65 d
- Analog Devices · 22 open roles · median 14 d
- Renesas Electronics · 17 open roles · median 25 d
- onsemi · 16 open roles · median 113 d
- NXP Semiconductors · 15 open roles · median 85 d
How we counted: 282 open Analog IC Design (Analog Design) roles from 51 employers tracked in the SemiconductorJobs index, counted 30 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.