Staff Digital Physical Implementation and Integration Engineer - San Jose, CA, United States

Originally posted 13 August 2026 by the employer.

Own physical implementation and top-level integration of large digital designs in our NAND products.

About the role

As a Design Engineer, you will be responsible for designing and analyzing digital and analog circuits used in the development of memory products. You will own physical implementation and top-level integration of large digital designs in NAND products.

What you'll do

• Contribute to the development of new product opportunities by assisting with the overall design, layout, and optimization of Memory/Logic/Analog circuits.
• Lead and manage the layout process including floor-planning, placement, and routing.
• Perform verification processes with modeling and simulation using industry standard simulators.
• Perform top-level virtual flat placement to explore partitioning options and validate hierarchy quality.
• Implement full APR flow (init → floorplan → place → CTS → route → ECO → sign-off) on digital blocks.
• Automate flows in Tcl / SKILL / Python; extend internal make-based flow and contribute to shared analysis tooling and dashboards.

What you'll need

• 5+ years of digital physical design with at least one full tapeout owned end-to-end.
• Bachelor’s degree in Computer Engineering or Electrical Engineering.
• Strong static timing analysis and debug skills. Fluent with PrimeTime across MMMC and OCV/AOCV/POCV. Experience with ILM / ETM block abstractions and ECO fixing.
• Hands-on expertise with Cadence Innovus Hierarchical Flow or Synopsys ICC2 Design Planning – virtual flat, partitioning, pin optimization, budgeting, assembly.
• Proven experience with top-level digital integration flow end-to-end – driving a full-chip or large-partition design from planning through assembly and hand-off.
• Strong flat APR expertise with Innovus (or ICC2): floorplan, place, CTS, route, ECO, sign-off correlation.
• Synthesis proficiency with Design Compiler or Genus (WLM + topographical/physical); comfort with size_only, don't_touch, MBFF, scan, clock gating.
• Physical verification with Calibre: DRC, LVS, antenna, PERC; hierarchical vs. flat runs and waiver management.
• SDC authoring for multi-mode/multi-corner designs; ability to derive and validate block budgets from top-level planning.
• Fluent in Tcl and one of Python/Perl for flow automation.
• Working proficiency with general-purpose agentic AI applied to engineering work – AI-powered assistants, MCP-based tool integration, and workflow automation.
• Solid grasp of CMOS logic, standard cells, RC extraction, EM/IR, and low-power techniques (MV, power gating, retention).
• Linux/Unix, Git or similar VCS, Make-based flows.

Nice to have

• Master’s degree or Ph.D. in Computer Engineering or Electrical Engineering.
• Multi-partition SoC or memory top-level integration; experience driving ECOs across a hierarchy of 5+ blocks.
• Clock planning at the top level – clock distribution across partitions, mesh/H-tree hybrids, boundary skew budgeting.
• Memory (NAND/DRAM) or mixed-signal design experience.
• Familiarity with DFT/scan compression, JTAG, MBIST and their interaction with partitioning.
• Familiarity with EDA-vendor AI tools – Cadence Cerebrus / JedAI, Synopsys DSO.ai and copilots, or equivalent.
• Contributions to methodology or CAD tooling.

Skills: layout, floor-planning, placement, routing, APR flow, STA sign-off