Staff Digital Design Engineer - Chandler, United States
Originally posted 16 July 2026 by the employer.
About the role
As a Staff Digital Design Engineer at Renesas Electronics in Chandler, AZ, you will architect, design, and integrate low-power digital circuits for mixed-signal applications. The role focuses on complex mixed-signal data conversion and power management products in advanced process nodes.
What you'll do
- Design digital RTL in Verilog and SystemVerilog that meets timing, area, power, and specification requirements. - Participate across the mixed-signal design flow, including micro-architecture, design partitioning, timing constraint generation, synthesis, P&R hand-off, timing analysis, LINT, CDC, RDC, and UPF. - Integrate designs at the top level and run block-level and top-level RTL and gate-level simulations. - Support DFT strategy and implementation, review test cases, and assist with top-level testbench debug. - Collaborate with analog and verification engineers to develop pre-silicon test scenarios and support AMS, SystemVerilog, or Verilog-real behavioral models. - Support the full product lifecycle from concept to mass production, including design reviews, documentation, silicon evaluation, and device errata tracking.
What you'll need
- More than 10 years of digital design experience in wireless handheld, data conversion, or power management. - Degree-level qualification in Electrical Engineering, Electronics, Computer Engineering, Computer Science, or a related discipline. - Fluency in Verilog / SystemVerilog RTL for digital CMOS circuit design. - Strong understanding of ASIC design methodology, block-level and chip-level verification techniques, and Lint, CDC & RDC tools. - Proven ability to debug both RTL and gate-level simulations. - Willingness to travel domestically or internationally on short notice.
Nice to have
- Experience with Digital Signal Processing (DSP) concepts and hardware realizations. - Experience with methodology and flow automation using scripting. - Experience with mixed-signal design methodologies, developing design constraints, and hand-off to P&R. - Experience with STA, timing closure, power analysis, and optimization. - Experience with low-power design techniques, including clock and power gating (UPF). - Experience with advanced verification methodologies (UVM). - Experience with industry-standard protocols such as AMBA or I2C.
This role has been open 96 days — well above the 62-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1051
|
Median days open
62 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Renesas Electronics | All employers we track in this specialty (1051 roles · 105 employers) |
|---|---|---|
| Open roles in this specialty | 21 | 1051 |
| Open roles in the wider Digital Design & Verification family | 80 | 3261 · 116 employers |
| Median days open | 57 d | 62 d (−5 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Who's hiring in this category
- Qualcomm · 150 open roles · median 57 d
- Synopsys · 84 open roles · median 35 d
- AMD · 72 open roles · median 42 d
- Analog Devices · 49 open roles · median 53 d
- NXP Semiconductors · 42 open roles · median 89 d
- NVIDIA · 40 open roles · median 62 d
How we counted: 1051 open Digital/RTL Design (RTL Design) roles from 105 employers tracked in the SemiconductorJobs index, counted 21 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.