Staff Design Verification Engineer – High Performance CPU Core
Originally posted 13 September 2026 by the employer — open 4 days.
Drive verification of high-performance CPU core units.
About the role
This Staff individual-contributor role drives verification of high-performance CPU core units, focusing on key core areas like Frontend, Midcore, Load-Store Unit, and Hardware Prefetch within the CPU Design Verification organization.
What you'll do
- Own verification planning and execution for high-performance out-of-order CPU core areas (Frontend, Midcore, Load-Store Unit, Hardware Prefetch).
- Drive block-level and core-level verification planning, debug, coverage analysis, and closure for complex CPU features.
- Define verification strategies for challenging behaviors including instruction fetch, branch prediction, pipeline interactions, and memory consistency.
- Develop and maintain robust verification environments, checkers, scoreboards, assertions, stimulus, and coverage models.
- Partner with architecture and design teams to review specifications, identify ambiguity, and improve design debugability and verification quality.
- Drive efficient failure analysis and root-cause debug across specification, RTL, test content, and verification infrastructure.
What you'll need
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
- 7+ years of experience in ASIC, CPU/core, or SoC design verification.
- Strong hands-on experience with SystemVerilog and UVM-based verification.
- Direct experience with CPU/core verification and strong understanding of computer architecture and CPU microarchitecture.
- Experience in Frontend, Midcore, Load-Store Unit, memory ordering/consistency, or hardware prefetch verification.
- Strong knowledge of verification flow methodology, including test planning, constrained-random or directed stimulus generation, failure analysis, coverage analysis, and coverage closure.
- Strong debug skills and the ability to translate architectural intent into effective verification strategy and execution.
Nice to have
- Experience with out-of-order core verification.
- Experience using formal verification and/or emulation for high-risk or performance-sensitive verification problems.
- Experience collaborating with performance, compiler, system verification, and software teams.
- Familiarity with Python, C/C++, or other scripting/programming languages used for DV infrastructure and automation.
This role has been open 4 days — well below the 56-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1122
|
Median days open
56 d
|
Median salary
$192k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | SiFive | All employers we track in this specialty (1122 roles · 92 employers) |
|---|---|---|
| Open roles in this specialty | 51 | 1122 |
| Open roles in the wider Digital Design & Verification family | 82 | 3007 · 114 employers |
| Median days open | 44 d | 56 d (−12 d vs this employer) |
| Median salary (USD postings) | — | $192k |
Who's hiring in this category
- Qualcomm · 104 open roles · median 53 d
- AMD · 99 open roles · median 33 d
- NVIDIA · 90 open roles · median 65 d
- Micron Technology · 56 open roles · median 96 d
- Synopsys · 54 open roles · median 23 d
- SiFive (this employer) · 51 open roles · median 44 d
How we counted: 1122 open Design Verification (Design Verification) roles from 92 employers tracked in the SemiconductorJobs index, counted 17 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.