Staff Design Verification Engineer – CPU Core Verification (Vector) - United States

Originally posted 13 September 2026 by the employer — open 4 days.

Drive verification of RISC-V Vector Extension (RVV) and vector microarchitecture.

About the role

This Staff Design Verification Engineer will drive verification of high-performance CPU core functionality, with significant scope in RISC-V Vector Extension (RVV) and vector microarchitecture verification. This individual contributor role focuses on high-performance out-of-order CPU core development, spanning areas such as Frontend, Midcore, Load-Store Unit, Hardware Prefetch, and Vector Unit / vector microarchitectural interactions.

What you'll do

• Own verification planning and execution for high-performance out-of-order CPU core areas, from block-level through core-level integration and signoff.
• Drive verification strategy, test planning, debug, coverage analysis, and closure for complex CPU features and microarchitectural interactions.
• Define effective verification approaches for challenging behaviors like branch prediction, instruction fetch, pipeline interactions, hazard handling, and vector execution correctness.
• Drive verification of RVV and vector-unit functionality, including vector arithmetic, masking behavior, and scalar-vector interactions.
• Develop and maintain robust verification environments, checkers, scoreboards, assertions, stimulus, and coverage models.
• Contribute reusable methodology, automation, and infrastructure to improve productivity and verification quality.

What you'll need

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 7+ years of relevant experience in ASIC, CPU/core, or SoC design verification, with ownership of complex verification problems.
• Strong hands-on experience with SystemVerilog-based verification and modern verification methodologies.
• Direct experience with CPU/core verification and strong understanding of computer architecture and CPU microarchitecture.
• Experience in one or more CPU core areas such as Frontend, Midcore, Load-Store Unit, or Vector Unit verification.
• Strong knowledge of verification flow methodology, including test planning, stimulus generation, failure analysis, coverage analysis, and coverage closure.
• Familiarity with Python, C/C++, or similar scripting/programming languages used for DV infrastructure and automation.

Nice to have

• Direct experience with high-performance out-of-order CPU core verification.
• Direct experience with RISC-V Vector Extension (RVV), SIMD, or vector-processor verification.
• Experience verifying vector behaviors such as vector arithmetic, masking, reductions, and vector load/store functionality.
• Experience verifying vector memory behavior, including alignment, page-boundary conditions, exception handling, and cache/memory interactions.
• Experience verifying vector configuration and execution modes such as SEW, LMUL, VL, VSTART.
• Experience verifying complex CPU microarchitectural behaviors involving concurrency, replay, flush, or weak memory ordering.
• Experience developing high-value assertions, checkers, and scoreboards for control-heavy or ordering-sensitive CPU behavior.
• Experience using formal verification, emulation, or acceleration.
• Experience collaborating with performance, compiler, system verification, and software teams.
• Experience influencing verification methodology through reusable infrastructure, automation, or technical leadership.

Skills: CPU core verification, RISC-V Vector Extension, SystemVerilog, coverage analysis, microarchitectural interactions