Staff Design Verification Engineer – CPU Core Formal Verification - United States

Originally posted 13 September 2026 by the employer.

SiFive is seeking a Staff Design Verification Engineer to drive formal verification of CPU core functionality.

About the role

This role is for a Staff Design Verification Engineer to drive formal verification of high-performance CPU core functionality. You will apply formal methods to complex out-of-order CPU core microarchitecture, focusing on areas like frontend, midcore control logic, issue and commit behavior, load-store interactions, and clock-gating.

What you'll do

• Own formal verification planning and execution for high-performance out-of-order CPU core areas, from block-level proof strategy through signoff-oriented closure.
• Develop formal verification plans based on architectural intent and microarchitectural risk, including assumptions, assertions, covers, and abstraction strategy.
• Create and maintain scalable formal environments, property sets, checkers, harnesses, and proof infrastructure for complex CPU control, ordering, and interface behavior.
• Analyze proof failures, counterexamples, vacuity, over-constraint, and incompleteness, and drive fixes across RTL, properties, assumptions, and verification infrastructure.
• Partner closely with architecture, RTL, and simulation-focused DV engineers to review specifications and align formal results with broader verification goals.
• Contribute reusable formal methodology, automation, debug workflows, and infrastructure that improve productivity and verification quality across future CPU core programs.

What you'll need

• 7+ years of relevant experience in ASIC, CPU/core, or SoC design verification.
• Direct experience with CPU/core verification and solid understanding of computer architecture and CPU microarchitecture.
• Strong hands-on experience with formal verification for RTL, including assertion-based verification, proof analysis, abstraction techniques, and closure of non-trivial properties.
• Experience developing assertions and formal strategies for control-heavy, ordering-sensitive, or interface-sensitive hardware behavior.
• Strong debugging skills with the ability to root-cause issues across specification, RTL, properties, and verification infrastructure.
• Strong understanding of verification methodology, including test planning, failure analysis, coverage thinking, and signoff discipline.
• Familiarity with scripting or programming in Python, Perl, Tcl, or similar languages used for automation and infrastructure.

Nice to have

• Experience with out-of-order CPU core verification.
• Experience applying formal methods to CPU core areas such as frontend control, issue logic, scoreboarding, commit, LSU ordering behavior, MMU/TLB control, or power / clock-gating logic.
• Experience with formal techniques for safety, liveness, deadlock, forward progress, connectivity, reset, and microarchitectural consistency checks.
• Experience balancing formal and simulation approaches, including identifying when a problem is best solved through exhaustive proof versus dynamic verification.
• Experience improving formal convergence through abstraction, environment modeling, assume-guarantee decomposition, and scalable proof planning.
• Experience collaborating across architecture, RTL, formal, and design verification teams in a fast-moving CPU development environment.
• Experience mentoring engineers and influencing verification methodology beyond immediate ownership scope.

Skills: formal verification, CPU core functionality, assertion-based verification, property sets, proof infrastructure