Staff Design Verification Engineer - Austin, Texas, United States
Originally posted 15 April 2026 by the employer.
About the role
This role partners with digital and analog designers, systems and applications engineers, firmware/software teams, and manufacturing test to deliver mixed-signal IC solutions. You will be responsible for end-to-end functional verification across block-level and chip-level custom mixed-signal ASICs.
What you'll do
- Develop verification plans aligned with design and system requirements. - Perform functional verification of custom mixed-signal ASICs at block and chip level. - Design and implement UVM-based testbenches, including infrastructure, scoreboards, checkers, and assertions. - Create directed and constrained-random test suites to drive functional and code coverage closure. - Conduct failure analysis, regression triage, and debug, resolving functional and timing-related issues. - Run and debug gate-level simulations, including timing violations and back-annotation issues.
What you'll need
- Bachelor’s with 7+ years, Master’s with 5+ years, or PhD with 3+ years of relevant experience in Electrical Engineering, Computer Engineering, or a related field. - Significant industry experience in silicon design and/or ASIC verification. - Strong proficiency with HDLs including Verilog and/or VHDL. - Strong proficiency with HVLs including SystemVerilog with UVM (or OVM/AVM/Vera). - Solid understanding of digital design principles and system architecture. - Hands-on experience with testbench architecture, stimulus generation, regression execution and debug, and coverage closure.
Nice to have
- Experience verifying mixed-signal ASICs in complex SoC environments. - Knowledge of signal processing concepts relevant to mixed-signal designs. - Experience with SystemVerilog Assertions (SVA). - Exposure to or hands-on experience with formal verification, hardware emulation or acceleration, or software-driven verification. - Demonstrated ability to evaluate, debug, and improve verification flows and methodologies.
Skills: UVM, SystemVerilog, functional verification, testbenches, coverage closure, mixed-signal ASICs
This role has been open 192 days — well above the 65-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1259
|
Median days open
65 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Cirrus Logic | All employers we track in this specialty (1259 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 11 | 1259 |
| Open roles in the wider Digital Design & Verification family | 29 | 3310 · 115 employers |
| Median days open | 216 d | 65 d (+151 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: UVM, SystemVerilog, functional verification, testbenches, coverage closure, mixed-signal ASICs
Who's hiring in this category
- Qualcomm · 120 open roles · median 44 d
- NVIDIA · 93 open roles · median 65 d
- AMD · 92 open roles · median 54 d
- Synopsys · 65 open roles · median 40 d
- SiFive · 55 open roles · median 82 d
- Cadence Design Systems · 52 open roles · median 124 d
How we counted: 1259 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 25 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.