Staff Design Engineer, Power Management, Clock & Reset

Originally posted 11 November 2026 by the employer.

About the role

This role involves developing power management, voltage control, clock, and reset technologies for System-on-Chip (SoC) solutions. You will contribute to the micro-architecture, RTL design, and implementation of critical IP and subsystems for Arm-based systems.

What you'll do

• Develop the micro-architecture and RTL design of IP and subsystems supporting power management, voltage control, clock management, and reset functionality.
• Translate architectural requirements into detailed design specifications and implement solutions that meet functional, power, performance, area, and timing objectives.
• Design and integrate control logic for power-state transitions, clock and reset sequencing, and multi-domain SoC operation.
• Ensure design quality through RTL reviews, synthesis, timing analysis, lint, clock domain crossing (CDC), reset domain crossing (RDC), and power-aware checks.
• Work with verification and implementation teams on test planning, functional debug, integration activities, and resolution of design issues.
• Contribute to improvements in design methodologies, automation, and development flows.

What you'll need

• Strong understanding of SoC power management and digital control logic, including low-power design techniques, voltage and power domains, clock/reset control, and power-state transitions.
• Experience developing digital IP or subsystems, translating architectural requirements into micro-architecture specifications, and implementing RTL using Verilog or SystemVerilog.
• Strong understanding of synthesis, timing analysis, lint, clock domain crossing (CDC), reset domain crossing (RDC), and power-aware design methodologies.
• Demonstrated ability to independently own design deliverables, evaluate technical solutions, and troubleshoot engineering challenges.
• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

Nice to have

• Experience with Arm-based SoCs, Arm system architectures, or complex semiconductor IP development.
• Familiarity with Unified Power Format (UPF), RTL and gate-level power estimation, and power modeling.
• Exposure to physical implementation, design for test (DFT), functional verification, X-propagation, and gate-level simulation.
• Experience with scripting and automation using Python, Perl, Tcl, or similar languages.
• Familiarity with AI-assisted tools for hardware design, verification, or engineering automation.

Skills: RTL, SystemVerilog, power management, clock domain crossing, CDC, RDC

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