Staff ASIC Verification Engineer - Bangalore, Karnataka, India
Originally posted 7 September 2026 by the employer.
About the role
This role involves ensuring the functional correctness, robustness, and overall quality of semiconductor and SoC designs.
What you'll do
- Develop and execute comprehensive verification plans, ensuring high-quality results with coverage closure.
- Apply standard ASIC verification techniques, including test planning, testbench creation, code and functional coverage, directed and random stimulus generation, and assertions.
- Create and enhance testbenches using SystemVerilog (OVM/UVM) or other standard testbench languages, and implement reusable Verification IP (VIP) components.
- Demonstrate a solid understanding of ASIC design and verification methodologies, applying object-oriented programming principles and constraint random verification methodology.
- Work effectively with internal teams and external customers.
What you'll need
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
- 10 Years of experience in SoC/IP verification.
- Strong expertise in SystemVerilog, UVM, and advanced verification methodologies.
- Hands-on experience with ARM-based SoC architectures, AMBA protocols (AXI/AHB/APB), and system-level interactions.
- Proven ability to build reusable, scalable testbench architectures.
- Solid understanding of test planning, coverage-driven verification, and verification metrics.
- Experience with GLS, timing verification, and debug.
- Knowledge of power-aware verification (UPF/CPF).
- Strong scripting and automation skills (Python, Perl, Shell, Make, etc.).
- Exposure to AI/ML techniques applied to verification.
Nice to have
- Familiarity with industry standards (e.g., I2C/SPI).
- Experience with low-power verification using UPF (Unified Power Format).
- Knowledge of formal verification techniques.
Skills: SystemVerilog, UVM, testbench, coverage closure, constraint random verification
This role has been open 22 days — well below the 63-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1169
|
Median days open
63 d
|
Median salary
$188k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | onsemi | All employers we track in this specialty (1169 roles · 95 employers) |
|---|---|---|
| Open roles in this specialty | 15 | 1169 |
| Open roles in the wider Digital Design & Verification family | 57 | 3113 · 115 employers |
| Median days open | 59 d | 63 d (−4 d vs this employer) |
| Median salary (USD postings) | — | $188k |
Skills observed across this category: SystemVerilog, UVM, testbench, coverage closure, constraint random verification
Who's hiring in this category
- AMD · 104 open roles · median 39 d
- Qualcomm · 97 open roles · median 53 d
- NVIDIA · 86 open roles · median 70 d
- Synopsys · 62 open roles · median 23 d
- SiFive · 57 open roles · median 56 d
- NXP Semiconductors · 52 open roles · median 76 d
How we counted: 1169 open Design Verification (Design Verification) roles from 95 employers tracked in the SemiconductorJobs index, counted 29 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.