Staff ASIC STA Engineer - Sunnyvale, CA, United States
Originally posted 4 October 2026 by the employer.
About the role
This role involves leading ASIC physical STA design and engineering workflow development. You will drive optimization, implementation, and timing exploration workflows for full ASIC chip STA flow.
What you'll do
- Lead ASIC physical STA design and engineering workflow development.
- Guide and assist colleagues to improve frontend physical design with respect to STA at block level and full-chip.
- Drive optimization, implementation, and timing exploration workflows, including hierarchical STA, timing analysis, and clock analysis.
- Continuously innovate and improve scalable, reliable, high-performance systems and tools.
- Work closely with ASIC team members to understand and improve their workflows and EDA needs.
What you'll need
- 10+ years of hands-on ASIC engineering experience.
- Deep knowledge of VLSI/SoC chip physical design workflows.
- Experience with EDA tools like Cadence/Synopsys PrimeTime/Tempus.
- Knowledge of clock methodology and development of hierarchical constraints.
- Strong physical design knowledge for STA analysis and ability to write SDCs for high-speed IP interfaces such as PCIe, SerDes, and other multi-clock domain blocks.
- Experience leading and supporting backend design teams with understanding of STA timing issues, clock trees, routing, and timing ECO generation for block and full-chip levels.
- Understanding of Genus/Innovus tool usage with respect to STA.
- Bachelor’s or Master's degree in Computer Science, Computer Engineering, Electrical Engineering, or a related technical field.
Skills: ASIC physical STA, timing closure, PrimeTime, hierarchical STA, SDCs
This role has been open 5 days — well below the 60-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
671
|
Median days open
60 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Tensordyne | All employers we track in this specialty (671 roles · 78 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 671 |
| Open roles in the wider Physical Implementation family | 2 | 1485 · 107 employers |
| Median days open | 4 d | 60 d (−56 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: ASIC physical STA, timing closure, PrimeTime, hierarchical STA, SDCs
Who's hiring in this category
- Qualcomm · 130 open roles · median 38 d
- AMD · 59 open roles · median 21 d
- NVIDIA · 42 open roles · median 63 d
- Broadcom · 38 open roles · median 88 d
- Synopsys · 35 open roles · median 39 d
- Micron Technology · 25 open roles · median 78 d
How we counted: 671 open Physical Design (Physical Design) roles from 78 employers tracked in the SemiconductorJobs index, counted 9 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.