Staff Applications Engineer - Timing & Signoff
Originally posted 30 August 2026 by the employer.
About the role
This role involves deploying and supporting Synopsys signoff tools for advanced node SoCs and 3DICs, working directly with customers to diagnose and resolve static timing analysis, power integrity, signal integrity, and reliability challenges.
What you'll do
- Deploy and support Synopsys signoff tools including PrimeTime, RedHawk-SC, PrimeClosure, PTECO, Tweaker, and StarRC at semiconductor companies and foundries.
- Engage directly with customer design teams to diagnose and resolve static timing analysis, power integrity, signal integrity, and reliability signoff challenges.
- Own technical issues end to end, working proactively with assigned accounts to deliver solutions that unblock tapeouts.
- Collaborate with Synopsys product development teams to translate customer pain points and feature requests into actionable product enhancements.
- Support presales technical activities by demonstrating the Seascape platform and signoff solutions.
- Build and maintain a knowledge base of EDA best practices, deployment guides, and troubleshooting FAQs.
What you'll need
- 3-5 years of hands-on experience in semiconductor design, with expertise in static timing analysis, timing closure, ECO implementation, or power delivery network analysis at block or SoC level.
- Proven ability to provide technical support or applications engineering for timing signoff or power integrity domains, including direct customer interaction and issue resolution.
- Working proficiency with Synopsys signoff tools such as PrimeTime, RedHawk-SC, PrimeClosure, PTECO, Tweaker, or StarRC in real design environments.
- Strong scripting and programming skills in languages like Python, Tcl, or Perl.
- Experience with PDN implementation flows, advanced node design challenges, or 3DIC methodologies.
Nice to have
Skills: PrimeTime, RedHawk-SC, StarRC, static timing analysis, power integrity, signoff
This role has been open 43 days — well below the 82-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
687
|
Median days open
82 d
|
Median salary
$195k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Synopsys | All employers we track in this specialty (687 roles · 74 employers) |
|---|---|---|
| Open roles in this specialty | 65 | 687 |
| Open roles in the wider Physical Implementation family | 108 | 1463 · 108 employers |
| Median days open | 37 d | 82 d (−45 d vs this employer) |
| Median salary (USD postings) | — | $195k |
Skills observed across this category: PrimeTime, RedHawk-SC, StarRC, static timing analysis, power integrity, signoff
Who's hiring in this category
- Cadence Design Systems · 157 open roles · median 169 d
- Synopsys (this employer) · 65 open roles · median 37 d
- Micron Technology · 42 open roles · median 94 d
- Qualcomm · 41 open roles · median 65 d
- NVIDIA · 40 open roles · median 78 d
- GlobalFoundries · 30 open roles · median 48 d
How we counted: 687 open EDA/CAD Engineering (EDA Tools) roles from 74 employers tracked in the SemiconductorJobs index, counted 14 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.