Staff Applications Engineer, Synthesis and Formal Verification
Originally posted 21 October 2026 by the employer.
Guide customer design teams on RTL-to-netlist methodologies using Fusion Compiler, Design Compiler, RTL Architect, and Formality.
About the role
As a Staff Applications Engineer in the Technical Sales Group, you will own technical relationships with customer RTL, synthesis, formal verification, and physical design teams from flow evaluation through tapeout. The role focuses on synthesis and equivalence checking using tools such as Fusion Compiler, Design Compiler, RTL Architect, and Formality.
What you'll do
- Own technical relationships with customer design teams, acting as a technical partner for synthesis and equivalence checking tools. - Debug synthesis and Formality issues, reproduce problems, isolate root causes, and provide recommendations or escalate reproducible test cases to R&D. - Guide customers on RTL-to-netlist methodologies using Fusion Compiler, Design Compiler, RTL Architect, and Formality, covering hierarchy, datapath optimization, physical-aware synthesis, clock gating, and multi-bit registers. - Analyze synthesis results, timing reports, SDC constraint files, library characterization, and PPA metrics to optimize correlation with downstream implementation. - Create and maintain reusable Tcl scripts, reference flows, application notes, debug guides, and training materials. - Support technical evaluations, benchmarks, design reviews, and customer adoption of synthesis and formal verification technologies.
What you'll need
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent hands-on experience in ASIC design or EDA applications. - 5 or more years of hands-on experience in ASIC or SoC design, logic synthesis, formal equivalence checking, or EDA applications engineering, with at least one production design cycle or tapeout. - Strong working knowledge of Verilog or SystemVerilog RTL, logic synthesis fundamentals, timing constraints (SDC), standard-cell libraries, and RTL-to-netlist design flows. - Practical experience with formal equivalence checking tools, including setting up comparisons, investigating setup issues, and analyzing proof failures or inconclusive results. - Proficiency with Tcl scripting and Linux command-line environments to automate flows and parse reports.
Skills: Design Compiler, Fusion Compiler, Formality, synthesis, formal equivalence checking, Tcl
This role has been open 0 days — well below the 34-day median for Applications FAE roles.
Applications FAE · EDA Tools
|
Open roles in category
121
|
Median days open
34 d
|
Median salary
$182k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Synopsys | All employers we track in this specialty (121 roles · 11 employers) |
|---|---|---|
| Open roles in this specialty | 63 | 121 |
| Median days open | 31 d | 34 d (−3 d vs this employer) |
| Median salary (USD postings) | — | $182k |
Skills observed across this category: Design Compiler, Fusion Compiler, Formality, synthesis, formal equivalence checking, Tcl
Who's hiring in this category
- Synopsys (this employer) · 61 open roles · median 31 d
- Cadence Design Systems · 33 open roles · median 24 d
- Keysight Technologies · 9 open roles · median 57 d
- Renesas Electronics · 9 open roles · median 70 d
- Amazon · 2 open roles · median 12 d
- Arteris · 2 open roles · median 122 d
How we counted: 121 open Applications FAE (EDA Tools) roles from 11 employers tracked in the SemiconductorJobs index, counted 23 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.