Staff Application Engineer- Physical Design
Originally posted 8 September 2026 by the employer.
About the role
This role involves supporting customer engagements on Synopsys physical design tools and debugging complex physical design issues across the RTL-to-GDS flow. You will focus on achieving PPA targets on advanced node designs, including 7nm, 5nm, and below.
What you'll do
- Support customer engagements on Synopsys physical design tools including Fusion Compiler, ICC2, and Design Compiler
- Debug complex physical design issues across the RTL-to-GDS flow, including placement, CTS, routing, timing closure, and power optimization at 7nm, 5nm, and below
- Develop and deliver methodology recommendations tailored to customer design constraints and process technologies
- Run benchmarks and proof-of-concept flows to demonstrate tool capabilities, AI-driven optimization features, and advanced node methodologies
- Collaborate with R&D, product management, and field teams to translate customer pain points into product requirements
- Present technical content to customer engineering teams and management, translating tool capabilities into business outcomes
What you'll need
- Bachelor's degree in Electrical Engineering or equivalent with 7+ years of hands-on ASIC physical design experience, or Master's degree with 5+ years
- Deep experience with RTL-to-GDS flows using industry-standard tools, including placement, optimization, clock tree synthesis, and routing
- Strong working knowledge of Synopsys backend tools, specifically Fusion Compiler or ICC2, with hands-on experience in timing closure, macro placement, and routing at advanced nodes
- Proficiency with static timing analysis tools, particularly PrimeTime, including setup/hold analysis and noise analysis
- Solid understanding of advanced node design challenges at 7nm and below, including FinFET effects, multi-patterning, and electromigration
- Experience with logical and physical synthesis flows and AI-driven methodologies for optimization
Skills: physical design, RTL-to-GDS, Fusion Compiler, ICC2, timing closure
This role has been open 35 days — slightly above the 29-day median for Applications FAE roles.
Applications FAE · EDA Tools
|
Open roles in category
105
|
Median days open
29 d
|
Median salary
$162k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Synopsys | All employers we track in this specialty (105 roles · 11 employers) |
|---|---|---|
| Open roles in this specialty | 54 | 105 |
| Median days open | 26 d | 29 d (−3 d vs this employer) |
| Median salary (USD postings) | — | $162k |
Skills observed across this category: physical design, RTL-to-GDS, Fusion Compiler, ICC2, timing closure
Who's hiring in this category
- Synopsys (this employer) · 54 open roles · median 26 d
- Cadence Design Systems · 24 open roles · median 47 d
- Keysight Technologies · 9 open roles · median 49 d
- Renesas Electronics · 9 open roles · median 62 d
- AMD · 2 open roles · median 87 d
- Arteris · 2 open roles · median 114 d
How we counted: 105 open Applications FAE (EDA Tools) roles from 11 employers tracked in the SemiconductorJobs index, counted 15 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.