Staff Application Engineer
Originally posted 29 September 2026 by the employer.
Work with customers running Synopsys ZeBu emulation platforms.
About the role
This Staff Application Engineer role involves working directly with customers to deploy and optimize emulation solutions for SoC and ASIC verification projects. You will debug complex issues spanning hardware models, software interactions, and testbench integration.
What you'll do
- Work with customers to deploy and optimize emulation solutions for SoC and ASIC verification projects.
- Design emulation strategies tailored to customer architecture, testbench, and schedule constraints.
- Debug complex issues across hardware models, software interactions, and testbench integration.
- Build and deliver technical enablement sessions and workshops for customers and internal teams.
- Collaborate with product engineering teams to provide customer requirements and feature requests.
- Mentor engineers to build technical skills in emulation methodologies and customer engagement.
What you'll need
- 7+ years in applications engineering, hardware verification, or emulation support roles.
- Hands-on experience with emulation platforms such as Synopsys ZeBu, Mentor Veloce, or Cadence Palladium.
- Strong working knowledge of Verilog, SystemVerilog, or VHDL.
- Strong working knowledge of verification methodologies including UVM or OVM.
- Demonstrated ability to debug and optimize interactions between hardware models, testbenches, and emulation infrastructure.
- Solid understanding of SoC and ASIC architecture and verification environments.
- Experience with Python, Perl, or TCL for automation and workflow scripting.
Skills: emulation platforms, SoC/ASIC verification, UVM, SystemVerilog, customer support
This role has been open 8 days — well below the 63-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1206
|
Median days open
63 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Synopsys | All employers we track in this specialty (1206 roles · 95 employers) |
|---|---|---|
| Open roles in this specialty | 61 | 1206 |
| Open roles in the wider Digital Design & Verification family | 167 | 3183 · 114 employers |
| Median days open | 25 d | 63 d (−38 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: emulation platforms, SoC/ASIC verification, UVM, SystemVerilog, customer support
Who's hiring in this category
- Qualcomm · 111 open roles · median 42 d
- AMD · 102 open roles · median 49 d
- NVIDIA · 76 open roles · median 62 d
- Synopsys (this employer) · 61 open roles · median 25 d
- SiFive · 55 open roles · median 66 d
- Micron Technology · 52 open roles · median 98 d
How we counted: 1206 open Design Verification (Design Verification) roles from 95 employers tracked in the SemiconductorJobs index, counted 9 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.