Staff Analog Design Engineer, TX/RX Datapath - Santa Clara, United States
Originally posted 19 August 2026 by the employer.
About the role
You will own the transmit and receive datapath of the high-speed SerDes on d-Matrix's IO chiplet, driving blocks from specification through silicon characterization.
What you'll do
- Own transistor-level design of the SerDes transmit path, including output drivers (SST and/or CML), pre-driver, serializer stages, and transmit-side FFE. - Own transistor-level design of the receive front-end, including termination, ESD-aware input network, CTLE, VGA, samplers, and ADC-based front-ends. - Design and verify the equalization path (DFE and FFE architecture, tap resolution, and adaptation behavior) and derive block-level specifications from link budgets covering insertion loss, crosstalk, reflection, jitter, and BER targets. - Build the verification environment for your blocks using testbenches, PVT corner coverage, six-sigma Monte Carlo, transient noise, post-layout back-annotated simulation, and Verilog-A models. - Perform link and channel modeling in MATLAB or Python using S-parameter channel and package models, statistical eye and BER analysis, and equalization trade studies. - Drive layout in deep sub-micron nodes alongside layout and package/signal-integrity engineers, and take blocks through silicon bring-up and bench characterization using high-speed lab equipment.
What you'll need
- BS/MS/PhD in Electrical Engineering with 8+ years of hands-on analog and mixed-signal circuit design experience. - Demonstrated ownership of a SerDes transmit or receive datapath block through to working silicon in a high-speed link. - Deep knowledge of high-speed driver design, receive front-end design, equalization, and jitter and noise analysis decomposition and budgeting. - Circuit design experience in advanced FinFET or GAA process nodes with hands-on use of Cadence Virtuoso, Spectre, Monte Carlo/corner analysis, and post-layout simulation. - Silicon bring-up and bench debug experience using high-speed lab equipment such as scopes and BERTs.
Nice to have
- Die-to-die interconnect experience (UCIe, BoW, or proprietary D2D PHY), including short-reach, low-energy-per-bit links. - Experience with PAM4 signaling, DSP-based receiver architectures, and ADC-based front-ends. - Familiarity with UCIe, OIF CEI-112G/224G, IEEE 802.3, or PCIe Gen6/Gen7 specifications. - Experience porting a datapath block across process nodes. - IBIS-AMI model generation, or SerDes ATE and production test development. - Participation in or contribution to standards bodies.
Skills: SerDes, transmit path, receive front-end, equalization, transistor-level design, link modeling
This role has been open 65 days — below the 71-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
238
|
Median days open
71 d
|
Median salary
$177k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | d-Matrix | All employers we track in this specialty (238 roles · 47 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 238 |
| Open roles in the wider Analog & Mixed-Signal family | 3 | 1439 · 106 employers |
| Median days open | 65 d | 71 d (−6 d vs this employer) |
| Median salary (USD postings) | — | $177k |
Skills observed across this category: SerDes, transmit path, receive front-end, equalization, transistor-level design, link modeling
Who's hiring in this category
- Synopsys · 35 open roles · median 37 d
- AMD · 27 open roles · median 41 d
- Qualcomm · 21 open roles · median 65 d
- Cadence Design Systems · 20 open roles · median 147 d
- Micron Technology · 15 open roles · median 38 d
- Apple · 9 open roles · median 24 d
How we counted: 238 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 47 employers tracked in the SemiconductorJobs index, counted 23 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.