Staff Analog Design Engineer, SerDes Clocking - Santa Clara, United States

Originally posted 19 August 2026 by the employer.

About the role

This is a hands-on, transistor-level analog design role owning the clocking subsystem of the high-speed SerDes on an IO chiplet. You will personally carry designs from specification through silicon characterization, spanning PLL, DLL, phase interpolator, high-frequency clock distribution, and clock and data recovery (CDR) loops.

What you'll do

- Own transistor-level design of low-jitter frequency synthesis, including LC and/or ring PLL, loop filter, charge pump or digital loop, VCO, and divider chain. - Own the phase interpolator and phase rotation scheme, covering INL/DNL, glitch behavior, and interpolation resolution. - Design high-frequency clock distribution across the SerDes macro, including buffer chains, duty-cycle correction, quadrature generation and correction, skew control, and supply isolation. - Define and verify CDR architecture and loop dynamics, modeling loop behavior in MATLAB, Python, or equivalent, and correlating against transistor-level and silicon results. - Build verification environments with PSS/HB and transient noise analysis, PVT corner coverage, Monte Carlo, and post-layout back-annotated simulation, while providing Verilog-A models for full-chip verification. - Drive block layout in deep sub-micron nodes and lead silicon bring-up and bench characterization using phase noise analyzers, high-speed scopes, and BERTs.

What you'll need

- BS, MS, or PhD in Electrical Engineering with 5+ years of hands-on analog and mixed-signal circuit design experience. - Demonstrated ownership of a low-jitter PLL, phase interpolator, or CDR loop through silicon in a high-speed SerDes link. - Deep knowledge of PLL architecture, loop dynamics, VCO design, phase noise theory, and CDR loop analysis for jitter tolerance and jitter transfer. - Practical experience with jitter decomposition and budgeting methodology, including quantifying contributors in simulation. - Circuit design experience in advanced FinFET or GAA process nodes using Cadence Virtuoso, Spectre, Monte Carlo/corner analysis, and post-layout simulation. - Silicon bring-up and bench debug experience using phase noise analyzers, high-speed scopes, and BERTs.

Nice to have

- Die-to-die interconnect experience such as UCIe, BoW, or a proprietary D2D PHY. - Experience with forwarded-clock and matched-source-synchronous architectures alongside embedded-clock CDR. - Experience with digital and hybrid PLL/CDR implementations and associated digital calibration. - Familiarity with UCIe, OIF CEI-112G/224G, IEEE 802.3, or PCIe Gen6/Gen7 specifications. - Experience porting a clocking block across process nodes.

Skills: SerDes, PLL, CDR, jitter, phase interpolator, transistor-level design