STA Signoff Flow, Principal AE - San Jose, United States
$127,400 - $236,600 USD yearly
Originally posted 21 October 2026 by the employer.
Deploy and optimize static timing analysis and ECO flows using the Cadence Tempus Signoff tool.
About the role
As a Principal Application Engineer at Cadence Design Systems, you will perform static timing analysis, glitch, and noise analysis using the Tempus Signoff tool while executing and delivering timing analysis flows, ECO flows, CAD tools, and methodologies.
What you'll do
- Execute and lead Tempus timing signoff campaigns at existing and new customers. - Work on SDC constraints, advanced OCV/SOCV concepts, derates, PBA timing, and distributed and concurrent STA flows. - Perform timing correlation, tool feature benchmarking, constraints validation, and SPICE analysis across diverse process tech nodes and customer designs. - Deliver in-design timing ECO optimization solutions utilizing knowledge of place and route, clock tree, RC extraction, and UPF/CPF concepts. - Automate timing analysis and ECO flows using scripting languages including Perl, Tcl, and Python. - Collaborate with R&D and customers to enable timing analysis flows, deploy new tool features, and close bug fixes.
What you'll need
- 8+ years of experience in static timing analysis. - Experience leading and executing technical timing and correlation benchmark campaigns using Cadence Tempus. - Hands-on expertise delivering timing analysis and ECO flows. - Experience across physical design domains, including place and route, extraction, and SPICE. - Demonstrated scripting skills in Perl, Tcl, or Python for flow automation.
Skills: STA, Tempus, Timing Signoff, SDC, ECO, Tcl
This role has been open 1 day — well below the 34-day median for Applications FAE roles.
Applications FAE · EDA Tools
|
Open roles in category
121
|
Median days open
34 d
|
Median salary
$182k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Cadence Design Systems | All employers we track in this specialty (121 roles · 11 employers) |
|---|---|---|
| Open roles in this specialty | 33 | 121 |
| Median days open | 24 d | 34 d (−10 d vs this employer) |
| Median salary (USD postings) | — | $182k |
Skills observed across this category: STA, Tempus, Timing Signoff, SDC, ECO, Tcl
Who's hiring in this category
- Synopsys · 61 open roles · median 31 d
- Cadence Design Systems (this employer) · 33 open roles · median 24 d
- Keysight Technologies · 9 open roles · median 57 d
- Renesas Electronics · 9 open roles · median 70 d
- Amazon · 2 open roles · median 12 d
- Arteris · 2 open roles · median 122 d
How we counted: 121 open Applications FAE (EDA Tools) roles from 11 employers tracked in the SemiconductorJobs index, counted 23 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.