$165,000 - $175,000 USD yearly
Originally posted 3 November 2026 by the employer.
About the role
Ambarella is seeking an experienced Senior Verification Engineer to lead verification of advanced SoCs incorporating image and video processing, DSP, CPUs, and neural network accelerators. You will own verification strategies, develop scalable testbenches, drive coverage closure, and incorporate agentic AI verification flows.
What you'll do
- Define and execute verification strategies and test plans for complex digital IP, subsystems, and SoCs.
- Architect and develop reusable verification environments using SystemVerilog, UVM, Verilog, C/C++, and Python.
- Lead verification of image processing pipelines, video input, compression engines (including CABAC), DSP blocks, processor cores, and neural network accelerators.
- Develop constrained-random tests, reference models, assertions, scoreboards, and coverage models.
- Drive functional and code coverage closure and lead complex RTL and system-level debugging.
- Use, enhance, and extend agentic AI verification workflows for test generation, coverage analysis, failure triage, debugging, and regression automation.
What you'll need
- Master's degree in Electrical Engineering, Computer Engineering, or a related field.
- 5+ years of ASIC or SoC verification experience, or equivalent expertise.
- Deep knowledge of SystemVerilog, UVM, constrained-random verification, assertions, and coverage methodologies.
- Experience architecting complex verification environments and driving coverage closure.
- Strong understanding of digital design, computer architecture, and SoC integration.
- Advanced RTL and system-level debugging skills with strong programming skills in C/C++ and Python.
- Experience with commercial simulation, debugging, and coverage tools.
Nice to have
- Experience verifying complex video, image processing, DSP, or AI accelerator SoCs.
- Knowledge of video compression, memory subsystems, and processor architectures.
- Hands-on experience with AI-assisted verification, LLMs, or agentic AI workflows.
- Experience improving verification automation, regression infrastructure, and simulation efficiency.
- Familiarity with AI agent frameworks and their integration into engineering workflows.
- Experience mentoring engineers and driving verification methodology improvements.
Skills: SystemVerilog, UVM, coverage closure, testbench architecture, debugging
More semiconductor jobs: Ambarella jobs · Verification engineer jobs
This role has been open 2 days — well below the 57-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1317
|
Median days open
57 d
|
Category median salary (all employers)
$184k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Ambarella | All employers we track in this specialty (1317 roles · 99 employers) |
|---|---|---|
| Open roles in this specialty | 5 | 1317 |
| Open roles in the wider Digital Design & Verification family | 12 | 3499 · 120 employers |
| Median days open | 108 d | 57 d (+51 d vs this employer) |
| Median salary (USD postings) | — | $184k |
Skills observed across this category: SystemVerilog, UVM, coverage closure, testbench architecture, debugging
Who's hiring in this category
- Qualcomm · 117 open roles · median 49 d
- NVIDIA · 104 open roles · median 71 d
- Apple · 99 open roles · median 9 d
- AMD · 83 open roles · median 65 d
- Synopsys · 73 open roles · median 50 d
- SiFive · 58 open roles · median 63 d
How we counted: 1317 open Design Verification (Design Verification) roles from 99 employers tracked in the SemiconductorJobs index, counted 5 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.