Sr. Test Technician - Santa Clara, CA, United States
Originally posted 24 September 2026 by the employer.
About the role
This role supports the engineering team in maintaining, debugging, and repairing high-volume Automated Test Equipment (ATE), handlers, and loadboard hardware in a low-to-medium volume final test facility. The focus is on ensuring tool uptime, troubleshooting ATE hardware/DUT board interfaces, and performing preventative maintenance to support zero-defect automotive and industrial product shipments.
What you'll do
- Set up and run production machinery (ATE test handler loading).
- Load device trays/tubes into automated test handlers and clear mechanical jams to maintain high machine throughput (UPH).
- Inspect die surfaces, bond wires, and package leads under optical microscopes for cracks, chip-outs, or solder bridging.
- Record pass/fail yields, scrap counts, and test execution data in MES/ERP tracking software.
What you'll need
- High School Diploma or GED.
- 4–6 years in automated electronics or semiconductor back-end manufacturing.
- Working knowledge of MES software, inventory tracking (ERP/SAP), and basic MS Excel.
- Equipment knowledge of pick-and-place handlers, tape-and-reel sealers, label printers, and vacuum sealers.
Nice to have
- Associate Degree.
- Direct experience on major ATE platforms (e.g., Advantest V93000, Teradyne J750/UltraFLEX).
- Experience with industry-standard handlers/probers (e.g., TEL, Hon precision, Cohu).
This role has been open 0 days — well below the 23-day median for Silicon Test Engineering roles.
Silicon Test Engineering · DFT Test
|
Open roles in category
449
|
Median days open
23 d
|
Median salary
$184k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | SiTime | All employers we track in this specialty (449 roles · 72 employers) |
|---|---|---|
| Open roles in this specialty | 13 | 449 |
| Open roles in the wider Silicon Validation & Test family | 41 | 2135 · 111 employers |
| Median days open | 5 d | 23 d (−18 d vs this employer) |
| Median salary (USD postings) | — | $184k |
Who's hiring in this category
- Teradyne · 52 open roles · median 6 d
- Infineon Technologies · 36 open roles · median 31 d
- Renesas Electronics · 34 open roles · median 33 d
- Qualcomm · 27 open roles · median 19 d
- Micron Technology · 26 open roles · median 24 d
- AMD · 19 open roles · median 30 d
How we counted: 449 open Silicon Test Engineering (DFT Test) roles from 72 employers tracked in the SemiconductorJobs index, counted 24 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.