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AMD

Sr. System RTL Designer/Serdes Architect - CA, San Jose, United States

AMD US, CA, San Jose, United States Full-time 5 months ago
Digital Design & SoC Architecture

$203,000 - $348,000 USD yearly

Originally posted 26 May 2026 by the employer.

Focus on SerDes, fabrics, and memory subsystem architecture for CPU, GPU, and SoC designs.

About the role

AMD is seeking a senior-level System RTL designer with a background in IP architecture to guide architecture directions and complex IP integration. In this role, you will balance performance, power, and area across CPU, GPU, and SoC silicon designs.

What you'll do

- Define IP features and capabilities while owning architecture and micro-architecture requirements. - Drive technical specifications for IP blocks and provide technical direction to execution teams. - Align and optimize hardware silicon, firmware, and feature enablement for performance and power. - Own architecture analysis, resolve architecture-level issues, and support feature-change requests. - Partner with design teams on area/floorplan refinement, timing targets, verification test plans, and pre-silicon debug and performance sign-off. - Support post-silicon teams for performance tuning, power optimization, and issue debug.

What you'll need

- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. - Background in System RTL design and IP architecture. - Experience delivering silicon solutions balancing performance, power, and area (PPA).

Nice to have

- Expertise in systems and IP architecture with a focus on SerDes, fabrics, memory subsystems, I/O, clocking, or security. - Experience analyzing CPU/GPU/system-level performance bottlenecks and workloads. - Knowledge of power management, low power microarchitecture, and design methodologies.

Market context

This role has been open 150 days — well above the 63-day median for Digital/RTL Design roles.

Digital/RTL Design · RTL Design

Open roles in category
1084
Median days open
63 d
Median salary
$185k
See the full market breakdown ▾Category comparison, and who else is hiring
How AMD compares in Digital/RTL Design hiring
Metric AMD All employers we track in this specialty (1084 roles · 103 employers)
Open roles in this specialty 77 1084
Open roles in the wider Digital Design & Verification family 251 3328 · 115 employers
Median days open 42 d 63 d (−21 d vs this employer)
Median salary (USD postings) — $185k

Who's hiring in this category

  • Qualcomm · 160 open roles · median 60 d
  • Synopsys · 87 open roles · median 36 d
  • AMD (this employer) · 77 open roles · median 42 d
  • Analog Devices · 49 open roles · median 53 d
  • NXP Semiconductors · 42 open roles · median 92 d
  • NVIDIA · 39 open roles · median 64 d

How we counted: 1084 open Digital/RTL Design (RTL Design) roles from 103 employers tracked in the SemiconductorJobs index, counted 24 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.

Apply now
US, CA, San Jose, United States
On-site
Full-time
$203,000 - $348,000 USD yearly
5 months ago

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