Sr. Staff Test Engineering Manager - Santa Clara, CA, United States
Originally posted 22 June 2026 by the employer. Relisted by the employer on 22 September 2026.
About the role
As a Sr. Staff Test Engineering Manager, you will define and drive end-to-end test engineering strategy, execution, and delivery across wafer sort, characterization, and production for multi-site SOCs. The technical scope focuses on complex products including AI Compute, Server, and Network Processors using Advantest 93K and Teradyne tester platforms.
What you'll do
- Define and drive test engineering strategy across wafer sort, characterization, and production for multi-site SOCs on Advantest 93K and/or Teradyne tester platforms. - Establish best-known methods (BKMs) for post-silicon test development to enable first-time right execution. - Drive test architecture decisions and DFT/testability requirements in collaboration with Design and DFT teams. - Lead resource planning, staffing, and development of the test engineering team across multiple programs. - Partner with Design, DFT, Product Engineering, Hardware, and System Validation teams to resolve technical issues, optimize test programs, reduce test times, and improve yields. - Represent test engineering in program reviews, executive updates, and customer discussions while leading initiatives to adopt new tools and test methodologies.
What you'll need
- Bachelor’s degree in Electrical Engineering or related field with 10-15 years of related professional experience, or a Master’s degree with 7-12 years of semiconductor test engineering experience, including demonstrated leadership experience. - Expertise in Advantest 93K and/or Teradyne UltraFLEX ATE tester platforms. - Leadership experience in ATE testing, test methodology, silicon process, DFT/DFM, and high-speed digital testing. - Proven track record of leading NPI programs to successful production releases. - Working knowledge of C/C++, Perl, Python, Java, and Linux environments.
This role has been open 122 days — well above the 112-day median for Silicon Test Engineering roles.
Silicon Test Engineering · Silicon Validation
|
Open roles in category
187
|
Median days open
112 d
|
Median salary
$129k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Marvell Technology | All employers we track in this specialty (187 roles · 56 employers) |
|---|---|---|
| Open roles in this specialty | 9 | 187 |
| Open roles in the wider Silicon Validation & Test family | 59 | 2256 · 113 employers |
| Median days open | 120 d | 112 d (+8 d vs this employer) |
| Median salary (USD postings) | — | $129k |
Who's hiring in this category
- Teradyne · 14 open roles · median 117 d
- Qualcomm · 12 open roles · median 112 d
- Renesas Electronics · 12 open roles · median 105 d
- Infineon Technologies · 9 open roles · median 120 d
- Marvell Technology (this employer) · 9 open roles · median 120 d
- onsemi · 9 open roles · median 157 d
How we counted: 187 open Silicon Test Engineering (Silicon Validation) roles from 56 employers tracked in the SemiconductorJobs index, counted 23 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.