Sr. Staff/Principal PCIE Subsystem Architect - Santa Clara, California, United States of America
Qualcomm
Santa Clara, California, United States of America; Austin, Texas, United States of America; San Diego, United States of America, United States
2 months ago
Digital Design & SoC Architecture
$164,000 - $264,500 USD yearly
Originally posted 13 August 2026 by the employer.
About the role
This role involves defining and delivering high-performance I/O architectures for AI products in the datacenter, with a focus on PCIe, CXL, and UCIe interfaces.
What you'll do
- Define subsystem architecture and drive requirements from accelerator card to rack-scale deployments.
- Apply in-depth knowledge of PCIe, Ethernet, and other high-speed I/O interfaces.
- Understand PCIe ordering models, DMA flows, and high-speed serial interface behavior.
- Analyze PCIe Gen6/Gen7 requirements, including FLIT mode, PAM4 signaling, and system-level tradeoffs.
- Implement PCIe error containment and recovery mechanisms like AER, DPC, CRS, and FLR.
- Design I/O virtualization and isolation technologies such as SR-IOV, SIOV, and PF/VF isolation.
- Comprehend RAS, telemetry, reliability, and security requirements for server-class SoCs and accelerator subsystems.
- Evaluate scale-up and scale-out architectures, including PCIe switch fabrics and host-to-accelerator orchestration.
What you'll need
- Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience, OR Master's degree and 5+ years, OR PhD and 4+ years.
- 3 years of experience with high-performance designs involving PCIe, Ethernet, or other high-speed I/O interfaces.
- In-depth knowledge of PCIe, Ethernet, and other high-speed I/O interfaces used in datacenter and accelerator products.
- Strong understanding of PCIe ordering models, producer-consumer ordering, ARM ordering behavior, DMA flows, and high-speed serial interface behavior.
- Strong understanding of PCIe Gen6/Gen7 requirements, including FLIT mode, PAM4 signaling implications, link training, latency, error handling, and system-level tradeoffs.
- Experience with PCIe error containment and recovery mechanisms such as Advanced Error Reporting (AER), Downstream Port Containment (DPC), Configuration Request Retry Status (CRS), Function Level Reset (FLR), and reset separation.
- Experience with I/O virtualization and isolation technologies such as SR-IOV, SIOV, PF/VF isolation, and related software-visible requirements.
- Strong understanding of RAS, telemetry, reliability, and security requirements for server-class SoCs and accelerator subsystems.
- Good knowledge of scale-up and scale-out architectures, including PCIe switch fabrics, NIC connectivity, host-to-accelerator orchestration, and rack-level deployment considerations.
Nice to have
- Good understanding of PCIe integrity, security, and confidential-compute features such as IDE, DOE/SPDM, TDISP, SR-IOV, and SIOV.
- Strong familiarity with PCIe CEM standards, add-in card deployment constraints, retimers, signal-integrity considerations, and system-level validation flows.
- Good understanding of emerging AI interconnect standards and ecosystems such as UCIe, UALink/UAL, and UEC.
- Good understanding of PCIe firmware, BIOS/UEFI, operating-system, driver, and system-software requirements.
- Good understanding of high-speed SerDes and PHY technologies, including PCIe PHY, Ethernet PHY, PAM4 signaling, and power/performance tradeoffs.
- Good knowledge of server SoC architectures with emphasis on security, RAS, virtualization, IOMMU/SMMU, DMA, address translation, and telemetry.
Skills: PCIe, high-speed I/O, datacenter, accelerator products, SoC architectures
Market context
This role has been open 65 days — well below the 78-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
474
|
Median days open
78 d
|
Median salary
$238k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (474 roles · 65 employers) |
|---|---|---|
| Open roles in this specialty | 73 | 474 |
| Open roles in the wider Digital Design & Verification family | 381 | 3202 · 115 employers |
| Median days open | 87 d | 78 d (+9 d vs this employer) |
| Median salary (USD postings) | — | $238k |
Skills observed across this category: PCIe, high-speed I/O, datacenter, accelerator products, SoC architectures
Who's hiring in this category
- Qualcomm (this employer) · 75 open roles · median 85 d
- NVIDIA · 56 open roles · median 70 d
- Apple · 36 open roles · median 11 d
- AMD · 34 open roles · median 59 d
- Arm Holdings · 27 open roles · median 114 d
- Micron Technology · 22 open roles · median 106 d
How we counted: 474 open SoC/Chip Architecture (SOC Architecture) roles from 65 employers tracked in the SemiconductorJobs index, counted 17 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.