Sr. Staff Packaging Engineer- Process Package Integrity & Bumping - San Diego, California, United States of America
Process & Device Engineering
Originally posted 25 September 2026 by the employer.
About the role
This role involves driving technology development and new product introduction for wafer bumping (Far-BEOL) process integration, qualification, and high-volume readiness.
What you'll do
- Define bumping process flows (passivation/UBM/RDL/bump) and establish process windows and controls.
- Lead DOE-based optimization and partner with suppliers to improve yield, reliability, and cost.
- Collaborate with foundry FBEOL teams, bumping/assembly partners, and internal teams to deliver bumping solutions for advanced packaging.
- Lead bumping house/line bring-up, qualification, and ongoing performance management.
- Manage supplier relationships for external bumping houses/OSATs, including KPI definition and continuous improvement programs.
- Interface with foundries and bumping houses on process integration, change control, line qualification, and multi-source expansion.
What you'll need
- Expertise in Far-BEOL bumping process modules and integration, including passivation openings, UBM, RDL, solder/Cu pillar bump formation.
- Deep knowledge of flip-chip bump design intent and assembly interactions (bump metallurgy, pitch scaling, coplanarity, warpage interactions).
- Strong technical skills in bumping process/material/equipment characterization (metrology and inline controls), failure analysis, DOE design, statistical data analysis, and FMEA.
- Experience leading bumping process qualification and production release activities (process window definition, control plans/SPC, GR&R, and risk mitigation).
- Proven track record enabling package development through robust bumping solutions for flip-chip, RDL/fan-out RDL, and advanced packaging technologies (2.5D/3DIC).
- Expertise in manufacturing execution for Far-BEOL bump structures and bump line operations, including new bumping line bring-up, tooling/equipment qualification, and production ramp.
- Experience with chip and substrate design tools such as Calibre, Virtuoso, CAD, SiP, and GDS.
- Minimum of 8–10 years hands-on experience in silicon interconnect process, bumping and/or RDL process, new technology qualification and production.
Market context
This role has been open 1 day — well below the 57-day median for Process Integration roles.
Process Integration · Advanced Packaging
|
Open roles in category
74
|
Median days open
57 d
|
Median salary
$174k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (74 roles · 20 employers) |
|---|---|---|
| Open roles in this specialty | 3 | 74 |
| Open roles in the wider Process, Fab & Equipment family | 48 | 9460 · 108 employers |
| Median days open | 51 d | 57 d (−6 d vs this employer) |
| Median salary (USD postings) | — | $174k |
Who's hiring in this category
- Micron Technology · 13 open roles · median 110 d
- Intel Corporation · 12 open roles · median 25 d
- GlobalFoundries · 10 open roles · median 96 d
- Applied Materials · 8 open roles · median 33 d
- Renesas Electronics · 7 open roles · median 12 d
- Lumilens · 4 open roles · median 51 d
How we counted: 74 open Process Integration (Advanced Packaging) roles from 20 employers tracked in the SemiconductorJobs index, counted 27 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Process, Fab & Equipment family row. Figures refresh nightly.