Originally posted 6 October 2026 by the employer.
About the role
This role involves driving the physical implementation of high-performance SoCs through the complete RTL-to-GDSII flow.
What you'll do
- Own and drive end-to-end physical design implementation, including floor planning, synthesis, placement, Clock Tree Synthesis (CTS), and routing.
- Fine-tune design for Power, Performance, and Area (PPA) targets using multi-voltage domains, power gating (UPF), and datapath optimization.
- Drive Static Timing Analysis (STA) across multiple corners and operating modes, resolving setup/hold violations, signal integrity issues, and clock domain crossing constraints.
- Execute Design Rule Checks (DRC), Layout Versus Schematic (LVS), electromigration/IR drop (EMIR) analysis, and Equivalence Checking (LEC/Formality).
- Collaborate with RTL (Frontend), DFT, and Signoff teams for optimal PPA.
- Automate flows and improve design methodologies using Tcl, Python, or Perl scripting.
What you'll need
- 10+ years of experience in Physical design implementation.
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
- Extensive experience in physical design PPA activities, including floorplanning, placement, clock tree synthesis, routing, and timing closure.
- Good understanding of EDA tools such as Fusion Compiler, Innovus, Primetime, Tempus, VCLP, LEC, Calibre, Red Hawk.
- Strong understanding of static timing analysis, power analysis, and signal integrity analysis.
Nice to have
- Experience in mentoring and coaching junior engineers.
Skills: RTL-to-GDSII, PPA optimization, timing closure, STA, DRC/LVS
This role has been open 21 days — well below the 66-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
682
|
Median days open
66 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Renesas Electronics | All employers we track in this specialty (682 roles · 80 employers) |
|---|---|---|
| Open roles in this specialty | 15 | 682 |
| Open roles in the wider Physical Implementation family | 41 | 1507 · 111 employers |
| Median days open | 56 d | 66 d (−10 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: RTL-to-GDSII, PPA optimization, timing closure, STA, DRC/LVS
Who's hiring in this category
- Qualcomm · 126 open roles · median 49 d
- AMD · 61 open roles · median 29 d
- Intel Corporation · 40 open roles · median 19 d
- Synopsys · 38 open roles · median 41 d
- Broadcom · 37 open roles · median 102 d
- NVIDIA · 37 open roles · median 69 d
How we counted: 682 open Physical Design (Physical Design) roles from 80 employers tracked in the SemiconductorJobs index, counted 27 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.