Sr Staff Engineer-DFT
Originally posted 5 November 2026 by the employer.
About the role
Marvell is seeking a Senior Staff DFT Engineer in Santa Clara to set up the methodology and flow for optical digital signal processor (ODSP) ASICs. The role focuses on defining DFT architecture, IP integration, and sign-off on TSMC advanced process nodes.
What you'll do
- Define DFT architecture and implementation for chip blocks, including hierarchical DFT, test modes, and test clocking.
- Plan, partition, and integrate IP-level DFT for SerDes, PLL, memories, and third-party IP.
- Drive ATPG coverage, test-time, and pattern-count targets while optimizing compression and power during test.
- Lead DFT sign-off including DRC, simulation, timing, equivalence, and handoff to physical design (PD) and ATE.
- Debug silicon through failure isolation, diagnosis, and yield learning in collaboration with Product and Test engineering teams.
- Mentor junior engineers, review technical work, and coordinate across design, verification, PD, and test.
What you'll need
- BS in EE/CE with 8+ years or MS in EE/CE with 5+ years of DFT experience on complex SoCs, with multiple tape-outs and silicon bring-ups.
- Deep expertise in scan, compression, ATPG fault models, MBIST/repair, JTAG, and at-speed test.
- Strong DFT timing and STA knowledge.
- Proven experience with independent problem-solving and mentoring junior engineers.
Nice to have
- Experience with advanced nodes (7nm and below).
- Experience with high-speed SerDes or DSP products.
More semiconductor jobs: Marvell Technology jobs · DFT engineer jobs · Santa Clara jobs
This role has been open 0 days — well below the 55-day median for DFT Engineering roles.
DFT Engineering · DFT Test
|
Open roles in category
279
|
Median days open
55 d
|
Category median salary (all employers)
$206k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Marvell Technology | All employers we track in this specialty (279 roles · 55 employers) |
|---|---|---|
| Open roles in this specialty | 7 | 279 |
| Open roles in the wider Digital Design & Verification family | 41 | 3488 · 119 employers |
| Median days open | 8 d | 55 d (−47 d vs this employer) |
| Median salary (USD postings) | — | $206k |
Who's hiring in this category
- AMD · 37 open roles · median 54 d
- NVIDIA · 23 open roles · median 54 d
- Qualcomm · 22 open roles · median 84 d
- Broadcom · 21 open roles · median 2 d
- NXP Semiconductors · 20 open roles · median 54 d
- Synopsys · 19 open roles · median 34 d
How we counted: 279 open DFT Engineering (DFT Test) roles from 55 employers tracked in the SemiconductorJobs index, counted 5 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.