Sr. Staff Engineer, CPU (Front-End) Verification - Austin, Texas, United States
$100,000 - $500,000 USD yearly
Originally posted 4 September 2026 by the employer.
Tenstorrent is developing a high performance RISC-V CPU.
About the role
This role involves contributing to the unit-level verification of Tenstorrent's RISC-V CPU front end, including instruction fetch, branch prediction, and surrounding fetch control structures.
What you'll do
- Build and maintain UVM testbenches for instruction fetch units, branch predictors, and related sub-blocks.
- Develop constrained-random and directed tests targeting speculation depth, misprediction/redirect flows, fetch bubbles, and cache/TLB interactions.
- Develop and maintain C++ reference models and predictors that integrate into the verification framework for cycle-accurate or transaction-level checking.
- Execute verification plans, track functional and code coverage metrics, and ensure edge cases are verified.
What you'll need
- Experience verifying CPU front-end blocks—such as instruction fetch, branch predictors (BTB, TAGE, RAS), instruction caches/TLBs, or decode—using SystemVerilog, UVM, and C++.
- Experience building unit testbench environments with precise stimulus and checking.
- Pragmatic approach to building transactors, predictors, and scoreboards that can be reused across verification levels.
- Work alongside RTL designers to trace and fix misspeculation, redirect, and edge-case fetch bugs.
Skills: Design Verification Engineer, RISC-V CPU front end, UVM testbenches, stimulus generation, functional and code coverage
This role has been open 41 days — well below the 65-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1192
|
Median days open
65 d
|
Median salary
$186k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Tenstorrent | All employers we track in this specialty (1192 roles · 95 employers) |
|---|---|---|
| Open roles in this specialty | 12 | 1192 |
| Open roles in the wider Digital Design & Verification family | 28 | 3189 · 115 employers |
| Median days open | 141 d | 65 d (+76 d vs this employer) |
| Median salary (USD postings) | — | $186k |
Skills observed across this category: Design Verification Engineer, RISC-V CPU front end, UVM testbenches, stimulus generation, functional and code coverage
Who's hiring in this category
- Qualcomm · 106 open roles · median 42 d
- AMD · 99 open roles · median 55 d
- NVIDIA · 82 open roles · median 57 d
- Synopsys · 63 open roles · median 30 d
- SiFive · 54 open roles · median 72 d
- Cadence Design Systems · 50 open roles · median 114 d
How we counted: 1192 open Design Verification (Design Verification) roles from 95 employers tracked in the SemiconductorJobs index, counted 15 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.