Sr Staff Engineer - Analog Design
Originally posted 5 August 2026 by the employer.
Join Synopsys to work on Multi-Gbps SERDES IP for data centers, automotive networks, and AI accelerators.
About the role
As a Sr Staff Engineer - Analog Design, you will architect and design analog and mixed-signal circuits for Multi-Gbps SERDES IP. This role focuses on advanced FinFET and gate-all-around process nodes for data centers, automotive networks, and AI accelerators.
What you'll do
- Review high-speed SerDes standards (PCIe, Ethernet, USB, CXL) and translate them into transceiver architectures and sub-block specifications for Multi-Gbps NRZ and PAM4 designs.
- Architect and design analog and mixed-signal circuits including TX drivers, RX front-ends, adaptive equalizers, PLLs, DLLs, bandgap references, regulators, oscillators, and ADC/DAC blocks.
- Collaborate with digital design teams on analog and digital co-design, calibration loops, adaptation algorithms, and timing handoff.
- Guide layout engineers for physical implementation, parasitics minimization, process variation management, and robust post-silicon performance.
- Present simulation results, design trade-offs, and architectural decisions in internal reviews, customer meetings, and industry panel discussions.
- Document design features, simulation methodologies, test plans, and characterization results, and support post-silicon bring-up and debug.
What you'll need
- MTech or MS with 8+ years or BTech or BS with 10+ years of hands-on analog IC design experience in Electrical Engineering, Computer Engineering, or a related field.
- Proven track record of CMOS tape-outs in FinFET technologies with demonstrable experience in Multi-Gbps high-speed designs using NRZ and PAM4 modulation.
- Deep expertise in SERDES sub-circuit design including TX drivers, RX front-ends, adaptive equalizers, PLLs, DLLs, bandgap references, regulators, oscillators, and data converters.
- Strong understanding of analog and digital co-design, calibration and adaptation algorithms, and timing handoff between analog and digital domains.
- Proficiency with schematic entry, physical layout collaboration, design verification tools, and SPICE simulators such as Spectre or HSPICE.
- Experience with scripting languages such as TCL, PERL, or MATLAB for post-processing simulation data and automating design tasks.
- Solid grounding in system-level budgeting for jitter, amplitude, and noise, and familiarity with signal integrity challenges including packaging parasitics, crosstalk, and channel loss.
Nice to have
- Experience with ESD protection.
- Experience with custom digital design.
- Experience with design-for-reliability considerations such as electromigration, IR drop, aging, and self-heating.
Skills: SERDES, PAM4, FinFET, PLL, jitter budget
This role has been open 54 days — well below the 76-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
239
|
Median days open
76 d
|
Median salary
$177k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Synopsys | All employers we track in this specialty (239 roles · 49 employers) |
|---|---|---|
| Open roles in this specialty | 26 | 239 |
| Open roles in the wider Analog & Mixed-Signal family | 36 | 1385 · 107 employers |
| Median days open | 44 d | 76 d (−32 d vs this employer) |
| Median salary (USD postings) | — | $177k |
Skills observed across this category: SERDES, PAM4, FinFET, PLL, jitter budget
Who's hiring in this category
- AMD · 28 open roles · median 64 d
- Synopsys (this employer) · 26 open roles · median 44 d
- Qualcomm · 20 open roles · median 58 d
- Cadence Design Systems · 18 open roles · median 181 d
- Apple · 12 open roles · median 7 d
- NVIDIA · 11 open roles · median 116 d
How we counted: 239 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 49 employers tracked in the SemiconductorJobs index, counted 30 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.